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參數(shù)資料
| 型號： | M48T128V-85CS1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 0 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | PLASTIC, SO-44 |
| 文件頁數(shù)： | 13/30頁 |
| 文件大?。?/td> | 162K |
| 代理商： | M48T128V-85CS1 |
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M48T129Y, M48T129V
20/30
Figure 14. Back-up Mode Alarm Waveforms
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
1FFF7h. Bits BMB4-BMB0 store a binary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five-bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is a function of the select-
ed resolution.
If the processor does not reset the timer within the
specified period, the M48T129Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FFF0h). The
most significant bit of the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a ’0,’
the watchdog will activate the IRQ/FT pin when
timed-out. When WDS is set to a ’1,’ the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT Bit
will reset to a ’0’ at the end of a Watchdog time-out
when the WDS Bit is set to a ’1.’ The watchdog tim-
er can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI); or
2. the microprocessor can perform a WRITE of the
Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to VSS if not used. The watchdog
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec-
tively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
“00h” needs to be written to the Watchdog Regis-
ter in order to clear the IRQ/FT pin. This will also
disable the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
1FFF0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
AI01678C
VCC
IRQ/FT
HIGH-Z
VPFD (max)
VPFD (min)
AFE bit in Interrupt Register
AF bit in Flags Register
HIGH-Z
VSO
tREC
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T128V-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T128V-85PM1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T128VPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T128Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| M48T128Y_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 1 Mbit (128 Kb x 8) TIMEKEEPER?? SRAM |
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