參數(shù)資料
型號(hào): M48T129Y-70CS1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: PLASTIC, SO-44
文件頁(yè)數(shù): 11/30頁(yè)
文件大?。?/td> 162K
代理商: M48T129Y-70CS1
19/30
M48T129Y, M48T129V
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-4.
The IRQ/FT output is cleared by a READ to the
Flags Register as shown in Figure 13. A subse-
quent READ of the Flags Register will reset the
Alarm Flag (D6; Register 1FFF0h).
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T129Y/V was in the deselect mode
during power-up. Figure 14, page 20 illustrates the
back-up mode alarm timing.
Figure 13. Alarm Interrupt Reset Waveform
Table 12. Alarm Repeat Mode
RPT4
RPT3
RPT2
RPT1
Alarm Activated
1111
Once per Second
1110
Once per Minute
1100
Once per Hour
1000
Once per Day
1000
Once per Month
AI02581
AD0-AD7
ACTIVE FLAG BIT
ADDRESS 1FF0h
IRQ/FT
HIGH-Z
15ns Min
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