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參數(shù)資料
| 型號： | M48T201Y-70MHTR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | 1 TIMER(S), REAL TIME CLOCK, PDSO44 |
| 封裝： | PLASTIC, SOIC-44 |
| 文件頁數(shù)： | 5/35頁 |
| 文件大?。?/td> | 688K |
| 代理商： | M48T201Y-70MHTR |
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M48T201Y, M48T201V
Data Retention Mode
With valid VCC applied, the M48T201Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T201Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
VCC falls between VPFD (max) and VPFD (min).
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
remain active until VCC returns to nominal levels.
External RAM access is inhibited in a similar man-
ner by forcing ECON to a high level. This level is
within 0.2V of the VBAT. ECON will remain at this
level as long as VCC remains at an out-of-toler-
ance condition. When VCC falls below the level of
the battery (VBAT), power input is switched from
the VCC pin to the SNAPHAT
battery and the
clock registers are maintained from the attached
battery supply. External RAM is also powered by
the SNAPHAT battery. All outputs except GCON,
ECON, RST, IRQ/FT and VOUT, become high im-
pedance. The VOUT pin is capable of supplying
100A of current to the attached memory with less
than 0.3V drop under this condition. On power up,
when VCC returns to a nominal value, write protec-
tion continues for 200ms (max) by inhibiting ECON.
The RST signal also remains active during this
time (see Figure 15., page 27).
Note: Most low power SRAMs on the market to-
day can be used with the M48T201Y/V TIME-
KEEPER SUPERVISOR. There are, however
some criteria which should be used in making the
final choice of an SRAM to use.
The SRAM must be designed in a way where the
chip enable input disables all other inputs to the
SRAM. This allows inputs to the M48T201Y/V and
SRAMs to be “Don't care” once VCC falls below
VPFD (min). The SRAM should also guarantee
data retention down to VCC = 2.0V. The chip en-
able access time must be sufficient to meet the
system needs with the chip enable (and output en-
able) output propagation delays included.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T201Y-80MH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V TIMEKEEPER? supervisor |
| M48T201Y-80MH1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V TIMEKEEPER? supervisor |
| M48T201Y-80MH1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V TIMEKEEPER? supervisor |
| M48T201Y-80MH1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V TIMEKEEPER? supervisor |
| M48T201Y-85MH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3V TIMEKEEPER㈢ supervisor |
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