參數(shù)資料
型號(hào): M48T212A-85MH1TR
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDSO44
封裝: HATLESS, PLASTIC, SOIC-44
文件頁數(shù): 4/30頁
文件大?。?/td> 155K
代理商: M48T212A-85MH1TR
M48T212A
12/30
READ Mode
The M48T212A executes a READ cycle whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the address
inputs (A3-A0) defines which one of the on-chip
TIMEKEEPER registers is to be accessed. When
the address presented to the M48T212A is in the
range of 0h-Fh, one of the on-board TIMEKEEP-
ER registers is accessed and valid data will be
available to the eight data output drivers within
tAVQV after the address input signal is stable, pro-
viding that the E and G access times are also sat-
isfied. If they are not, then data access must be
measured from the latter occurring signal (E or G)
and the limiting parameter is either tELQV for E or
tGLQV for G rather than the address access time.
When EX input is low, an external SRAM location
will be selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
Figure 7. READ Cycle Timing: RTC Control Signal Waveforms
Note: EX is assumed High.
AI02640
W
DQ7-DQ0
G
DATA OUT
VALID
ADDRESS
tAVAV
E
tELQV
tAVAV
READ
WRITE
DATA IN
VALID
DATA OUT
VALID
tAVQV
tWHAX
tAVWL
tELQX
tGLQV
tGHQZ
tWLWH
tAXQX
tGLQX
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