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參數(shù)資料
| 型號(hào)： | M48T37VMH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| 中文描述： | 3.3 - 5V的256千位的32KB的SRAM x8計(jì)時(shí)器 |
| 文件頁(yè)數(shù)： | 8/20頁(yè) |
| 文件大小： | 128K |
| 代理商： | M48T37VMH |
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M48T37Y, M48T37V
8/20
Figure 7. Write Enable Controlled, Write AC Waveform
AI00926
tAVAV
tWHAX
tDVWH
DATA INPUT
A0-A14
E
W
DQ0-DQ7
VALID
tAVWH
tAVEL
tWLWH
tAVWL
tWLQZ
tWHDX
tWHQX
WRITE MODE
The M48T37Y/37V is in the Write Mode whenever
W and E are low. Thestart of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enableor t
WHAX
from WriteEn-
able prior to the initiation of another read or write
cycle. Data-in must be valid t
DVWH
prior to the end
of write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by alow on Eand Ga low onW will
disable the outputs t
WLQZ
after W falls.
DATA RETENTION MODE
With valid V
CC
applied, the M48T37Y/37V oper-
ates as a conventional BYTEWIDE static RAM.
Should the Supply Voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as ”don’t care”.
Note
: Apower failure during a write cycle maycor-
rupt data at the currently addressed location, but
does not jeopardizethe rest of theRAM’s content.
At voltages below V
PFD
(min), the user can be as-
sured the memory willbe ina write protectedstate,
provided the V
CC
fall time is not less than t
F
.
TheM48T37Y/37V may respond to transient noise
spikes on V
CC
that reach intothe deselect window
during thetime the device is sampling V
CC
. There-
fore, decoupling of the power supply lines is rec-
ommended.
When V
CC
drops below V
SO
, the control circuit
switches power to the internal battery which pre-
serves data and powers the clock. The internal
button cell will maintain data in the M48T37Y/37V
for an accumulated period of at least 7 years at
room temperature when V
CC
is less than V
SO
. As
system power returns and V
CC
rises above V
SO
,
the battery is disconnected, and the power supply
is switched to external V
CC
. Normal RAM opera-
tion can resume t
REC
after V
CC
reaches V
PFD
(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48T37V-70MH1 | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37Y-70MH1 | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37V-10MH1 | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37Y-10MH1 | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37VSH | 3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48T37VSH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37Y | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37Y_10 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5.0 or 3.3 V, 256 Kbit (32 Kbit x 8) TIMEKEEPER?? SRAM |
| M48T37Y-10MH1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
| M48T37Y-10MH1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V-5V 256 Kbit 32Kb x8 TIMEKEEPER SRAM |
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