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參數(shù)資料
| 型號(hào)： | M48T559YSH |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Hook-Up Wire; Conductor Size AWG:24; No. Strands x Strand Size:Solid; Jacket Color:Yellow; Approval Bodies:UL, CSA; Approval Categories:UL AWM Style 1061; CSA AWM; Conductor Material:Copper; Jacket Material:Polyvinylchloride (PVC) RoHS Compliant: Yes |
| 中文描述： | 64千位8KB的x8 SRAM的計(jì)時(shí)與地址/數(shù)據(jù)復(fù)用 |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大小： | 147K |
| 代理商： | M48T559YSH |
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M48T559Y
6/18
Table 9. AC Characteristics
(T
A
= 0 to 70 °C; V
CC
= 4.5V to 5.5V)
Symbol
Parameter
M48T559Y
Unit
Min
Max
t
AS
Address Setup Time
20
ns
t
AH
Address Hold Time
0
ns
t
DS
Data Setup Time
60
ns
t
DH
Data Hold Time
0
ns
t
RLDV
Read Enable Access Time
70
ns
t
RLRH
R Pulse Width Low
70
ns
t
RHDZ
Read Enable High to Output High Z
25
ns
t
WLWH
W Pulse Width Low
50
ns
t
ELEH
E Pulse Width Low
50
ns
t
ASLASH
AS0, AS1 Pulse Width Low
15
ns
t
ASHRL
AS0, AS1 High to R Low
15
ns
t
ASHWL
AS0, AS1 High to W Low
15
ns
t
ELRL
Chip Enable Low to Read Enable Low
0
ns
t
EHDZ
Chip Enable High to Data Output Hi-Z
0
ns
t
ELWL
Chip Enable Low to Write Enable Low
0
ns
RAM OPERATION
Four control signals, AS0, AS1, R and W, are used
to access the M48T559Y. The address latches are
loaded from the address/data bus in response to
rising edge signals applied to the Address Strobe
0 (AS0) and Address Strobe 1 (AS1) signals. AS0
is used to latch the lower 8 bits of address, and
AS1 is used to latch the upper 5 bits of address.
It is not however necessary to follow any particular
order. The inputs are in parallel for the two ad-
dress bytes (upper and lower) and can be latched
in any order as long as the correct strobe is used.
It is necessary to meet the set-up and hold times
given in the AC specifications with valid address
information in order to properly latch the address.
If the upper and/or lower order addresses are cor-
rect from a prior cycle, it is not necessary to repeat
the address latching sequence.
A write operation requires valid data to be placed
on the bus (AD0-AD7), followed by the activation
of the Write Enable (W) line. Data on the bus will
be written to the RAM, provided that the write tim-
ing specifications are met. During a read cycle, the
Read Enable (R) signal is driven active. Data from
the RAM will become valid on the bus provided
that the RAM read access timing specifications are
met.
The W and R signals should never be active at the
same time. In addition, E must be active before
any control line is recognized (except for AD0-AD7
and AS0, AS1).
RESET INPUT
The M48T559Y provides two debounced inputs
which can generate an output Reset. The duration
and function of the Reset output is identical to a
Reset generated by a power cycle. Pulses shorter
than t
R1
and t
R2
will not generate a Reset condi-
tion (see Table 12 and Figure 13).
DATA RETENTION MODE
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
self when V
CC
falls within the V
PFD
(max), V
PFD
(min) window. All outputs become high imped-
ance, and all inputs are treated as "don't care."
Note:
A power failure during a write cycle may cor-
rupt data at the currently addressed location, but
does not jeopardize the rest of the RAM's content.
At voltages below V
PFD
(min), the user can be as-
sured the memory will be in a write protected state,
provided the V
CC
fall time is not less than t
F
.
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