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參數(shù)資料
| 型號(hào)： | M48Z02-200PC6TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| 中文描述： | 5V的，16千位（2KB的× 8）ZEROPOWER的SRAM |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 85K |
| 代理商： | M48Z02-200PC6TR |
Symbol
Parameter
M48Z02 / M48Z12
Unit
-70
-150
-200
Min
Max
Min
Max
Min
Max
t
AVAV
Write Cycle Time
70
150
200
ns
t
AVWL
Address Valid to Write Enable Low
0
0
0
ns
t
AVEL
Address Valid to Chip Enable Low
0
0
0
ns
t
WLWH
Write Enable Pulse Width
50
90
120
ns
t
ELEH
Chip Enable Low to Chip Enable High
55
90
120
ns
t
WHAX
Write Enable High to Address Transition
0
10
10
ns
t
EHAX
Chip Enable High to Address Transition
0
10
10
ns
t
DVWH
Input Valid to Write Enable High
30
40
60
ns
t
DVEH
Input Valid to Chip Enable High
30
40
60
ns
t
WHDX
Write Enable High to Input Transition
5
5
5
ns
t
EHDX
Chip Enable High to Input Transition
5
5
5
ns
t
WLQZ
Write Enable Low to Output Hi-Z
25
50
60
ns
t
AVWH
Address Valid to Write Enable High
60
120
140
ns
t
AVEH
Address Valid to Chip Enable High
60
120
140
ns
t
WHQX
Write Enable High to Output Transition
5
10
10
ns
Table 10. Write Mode AC Characteristics
(T
A
= 0 to 70
°
C or –40 to 85
°
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
WRITE MODE
The M48Z02/12 is in the Write Mode whenever W
and E are active. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enable or t
WHAX
from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid t
DVWH
prior to the end
of write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs t
WLQZ
after W falls.
7/12
M48Z02, M48Z12
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48Z02-70PC1 | 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC1TR | 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC6 | 5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC6TR | FILTER, FRONT END SAW, 868.30MHZ; Attenuation, 1 GHz:40dB; Attenuation, 10 MHz:55dB; Attenuation, 20 MHz:55dB; Bandwidth:.78MHz; Case style:QCC8C; Depth, external:5.0mm; Frequency, min:868.30Hz; Height:1.35mm; Insertion loss:2.7dB; RoHS Compliant: Yes |
| M48Z08-100MH1 | 64 Kbit 8Kb x 8 ZEROPOWER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z02-70PC1 | 功能描述:NVRAM 16K (2Kx8) 70ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲(chǔ)容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問(wèn)時(shí)間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| M48Z02-70PC1 | 制造商:STMicroelectronics 功能描述:IC NVRAM 10 YR BATTERY 16K 48Z02 |
| M48Z02-70PC1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
| M48Z02-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V, 16 Kbit (2Kb x 8) ZEROPOWER SRAM |
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