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參數(shù)資料
| 型號： | M48Z128Y-120PM1 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| 中文描述： | 1兆位的SRAM 128KB的x8 ZEROPOWER |
| 文件頁數(shù)： | 8/17頁 |
| 文件大?。?/td> | 106K |
| 代理商： | M48Z128Y-120PM1 |
M48Z128, M48Z128Y
8/17
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Note: Write Enable (W) = High.
AI01197
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A16
E
G
DQ0-DQ7
VALID
WRITE MODE
The M48Z128/128Y is in the Write Mode whenev-
er W and Eare active. The start of a write is refer-
enced from thelatter occurring falling edgeof W or
E. A write is terminated by the earlier rising edge
of W or E.
The addresses must be held valid throughout the
cycle. E or W must return high for minimum of t
E-
HAX
from E or t
WHAX
from W prior to the initiation
of anotherread or write cycle. Data-inmust be val-
id t
DVWH
prior to the end of write and remain valid
for t
WHDX
or t
EHDX
afterward. G should be kept
high during write cycles to avoid bus contention;
although, if the output bus has been activated by a
low on Eand G, a low on W will disable theoutputs
t
WLQZ
after W falls.
DATA RETENTION MODE
With valid V
CC
applied, the M48Z128/128Y oper-
ates as a conventional BYTEWIDE
TM
static RAM.
Should the supply voltage decay, the RAMwill au-
tomatically power-fail deselect, write protecting it-
self t
WP
after V
CC
falls below V
PFD
. All outputs
become highimpedance, and all inputs are treated
as ”don’t care.”
If power fail detection occurs during a valid ac-
cess, the memory cycle continues to completion.If
the memory cycle fails to terminate within the time
t
WP
, write protection takes place. When V
CC
drops
below V
SO
, the control circuit switches power to
the internal energy source which preserves data.
The internal coin cell will maintain data in the
M48Z128/128Y after the initial application of V
CC
for an accumulated period of at least 10 years
when V
CC
is less than V
SO
. As system power re-
turns and V
CC
rises above V
SO
, the battery is dis-
connected, and the power supply is switched to
external V
CC
. Writeprotection continues for t
ER
af-
ter V
CC
reaches V
PFD
to allow for processor stabi-
lization. After t
ER
, normal RAM operation can
resume.
For more information on Battery Storage Life refer
to the Application Note AN1012.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M48Z128Y-70PM1 | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128Y-85PM1 | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128-85CS1 | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128-70PM1 | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128-70CS1 | 1 Mbit 128Kb x8 ZEROPOWER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z128Y-70CS1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128Y-70PM1 | 功能描述:NVRAM 1M (128Kx8) 70ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
| M48Z128Y-85CS1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:1 Mbit 128Kb x8 ZEROPOWER SRAM |
| M48Z128Y85PM1 | 制造商:STMicroelectronics 功能描述: |
| M48Z128Y-85PM1 | 功能描述:NVRAM 1M (128Kx8) 85ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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