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參數(shù)資料
| 型號： | M48Z2M1-70PL9 |
| 廠商： | 意法半導體 |
| 英文描述： | 16 Mb 2Mb x 8 ZEROPOWER SRAM |
| 中文描述： | 16兆的2Mb × 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 102K |
| 代理商： | M48Z2M1-70PL9 |
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
0 to 70
°
C
T
STG
Storage Temperature (V
CC
Off)
–40 to 85
°
C
T
BIAS
T
SLD
(2)
Temperature Under Bias
–40 to 85
°
C
Lead Soldering Temperature for 10 seconds
260
°
C
V
IO
Input or Output Voltages
–0.3 to 7
V
V
CC
Supply Voltage
–0.3 to 7
V
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260
°
C for 10 seconds (total thermal budget not to exceed 150
°
C for longer than 30 seconds).
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Operating Modes
Table 2. Absolute Maximum Ratings
(1)
Mode
V
CC
E
G
W
DQ0-DQ7
Power
Deselect
4.75V to 5.5V
or
4.5V to 5.5V
V
IH
X
X
High Z
Standby
Write
V
IL
X
V
IL
D
IN
Active
Read
V
IL
V
IL
V
IH
D
OUT
Active
Read
V
IL
V
IH
V
IH
High Z
Active
Deselect
V
SO
to V
PFD
(min)
X
X
X
High Z
CMOS Standby
Deselect
≤
V
SO
X
X
X
High Z
Battery Back-up Mode
Notes
: X = V
IH
or V
IL
; V
SO
= Battery Back-up Switchover Voltage.
VSS
VCC
A19
AI02049
M48Z2M1
M48Z2M1Y
10
11
12
13
14
15
1
2
3
4
5
6
7
8
9
16
17
18
30
29
28
27
26
25
24
23
22
21
20
19
32
31
34
33
36
35
A1
A0
DQ0
DQ1
DQ2
A7
A6
A5
A4
A3
A2
A13
A8
A9
A11
G
A10
E
DQ7
DQ6
A15
A17
DQ5
DQ4
DQ3
A16
A14
A18
A12
W
A20
NC
NC
Figure 2. DIP Pin Connections
The M48Z2M1/2M1Y has its own Power-fail Detect
Circuit. The control circuitry constantly monitors the
single 5V supply for an out of tolerance condition.
When V
CC
is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system op-
erations brought on by low V
CC
. As V
CC
falls below
approximately 3V, the control circuitry connects the
batteries which sustain data until valid power re-
turns.
READ MODE
The M48Z2M1/2M1Y is in the Read Mode when-
ever W (Write Enable) is high and E (Chip Enable)
is low. The device architecture allows ripple-
through access of data from eight of 16,777,216
locations in the static storage array. Thus, the
unique address specified by the 21 Address Inputs
defines which one of the 2,097,152 bytes of data is
to be accessed. Valid data will be available at the
Data I/O pins within Address Access time (t
AVQV
)
after the last address input signal is stable, provid-
ing that the E (Chip Enable) and G (Output Enable)
access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
DESCRIPTION
(cont’d)
Warning:
NC = Not Connected.
2/12
M48Z2M1, M48Z2M1Y
相關PDF資料 |
PDF描述 |
|---|---|
| M48Z2M1Y-70PL9 | 16 Mb 2Mb x 8 ZEROPOWER SRAM |
| M48Z2M1 | 122 x 32 pixel format, Compact LCD size |
| M48Z2M1PL | 122 x 32 pixel format, Compact LCD size |
| M48Z2M1Y | 122 x 32 pixel format, Compact LCD size |
| M48Z2M1YPL | 122 x 32 pixel format, Compact LCD size |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z2M1PL | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:16 Mb 2Mb x 8 ZEROPOWER SRAM |
| M48Z2M1V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER SRAM |
| M48Z2M1V-701 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER SRAM |
| M48Z2M1V-70G | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5V or 3.3V, 16 Mbit (2Mb x 8) ZEROPOWER SRAM |
| M48Z2M1V-70PL1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:5 V or 3.3 V, 16 Mbit (2 Mb x 8) ZEROPOWER? SRAM |
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