參數(shù)資料
型號: M48Z2M1Y-70PL1
廠商: 意法半導(dǎo)體
英文描述: 16 Mb 2Mb x 8 ZEROPOWER SRAM
中文描述: 16兆的2Mb × 8 ZEROPOWER的SRAM
文件頁數(shù): 1/12頁
文件大小: 102K
代理商: M48Z2M1Y-70PL1
M48Z2M1
M48Z2M1Y
16 Mb (2Mb x 8) ZEROPOWER
SRAM
January 1998
1/12
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
INTEGRATED LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERIES
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
10 YEARS of DATA RETENTION in the
ABSENCE of POWER
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z2M1: 4.5V
V
PFD
4.75V
– M48Z2M1Y: 4.2V
V
PFD
4.50V
BATTERIES ARE INTERNALLY ISOLATED
UNTIL POWER IS APPLIED
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 2Mb x 8 SRAMs
DESCRIPTION
The M48Z2M1/2M1Y ZEROPOWER
RAM is a
non-volatile 16,777,216 bit Static RAM organized
as 2,097,152 words by 8 bits. The device combines
two internal lithium batteries, CMOS SRAMs and a
control circuit in a plastic 36 pin DIP long Module.
The ZEROPOWER RAM replaces industry stand-
ard SRAMs. It provides the nonvolatility of PROMs
without any requirement for special write timing or
limitations on the number of writes that can be
performed.
AI02048
21
A0-A20
W
DQ0-DQ7
VCC
M48Z2M1
M48Z2M1Y
G
VSS
8
E
Figure 1. Logic Diagram
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
36
1
PMLDIP36 (PL)
Module
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