參數(shù)資料
型號: M48Z2M1Y-70PL9
廠商: 意法半導體
英文描述: 16 Mb 2Mb x 8 ZEROPOWER SRAM
中文描述: 16兆的2Mb × 8 ZEROPOWER的SRAM
文件頁數(shù): 7/12頁
文件大?。?/td> 102K
代理商: M48Z2M1Y-70PL9
AI02052
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
DATA OUT
A0-A20
E
G
DQ0-DQ7
VALID
Figure 7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Note:
Write Enable (W) = High.
DATA RETENTION MODE
With valid V
CC
applied, the M48Z2M1/2M1Y oper-
ates as a conventional BYTEWIDE
static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself t
WP
after V
CC
falls below V
PFD
. All outputs
become high impedance, and all inputs are treated
as "don’t care."
If power fail detection occurs during a valid access,
the memory cycle continues to completion. If the
memory cycle fails to terminate within the time t
WP
,
write protection takes place. When V
CC
drops be-
low V
SO
, the control circuit switches power to the
internal energy source which preserves data.
The internal coin cells will maintain data in the
M48Z2M1/2M1Y after the initial application of V
CC
for an accumulated period of at least 10 years when
V
CC
is less than V
SO
. As system power returns and
V
CC
rises above V
SO
, the batteries are discon-
nected, and the power supply is switched to exter-
nal Vcc. Write protection continues for t
ER
after V
CC
reaches V
PFD
to allow for processor stabilization.
After t
ER
, normal RAM operation can resume.
For more information on Battery Storage life refer
to the Application Note AN1012.
7/12
M48Z2M1, M48Z2M1Y
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