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參數(shù)資料
| 型號： | M48Z30Y-100PM1 |
| 廠商： | 意法半導體 |
| 英文描述： | CMOS 32K x 8 ZEROPOWER SRAM |
| 中文描述： | 的CMOS 32K的× 8 ZEROPOWER的SRAM |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 100K |
| 代理商： | M48Z30Y-100PM1 |
Figure7. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
Note:
W = High.
Awriteis terminatedby theearlier risingedgeof W
or E. The addressesmust beheld validthroughout
the cycle. E or W mustreturn high forminimum of
t
EHAX
fromE or t
WHAX
fromWprior to the initiation
of anotherread orwritecycle.Data-inmustbevalid
t
DVWH
prior to the end of write and remain validfor
t
WHDX
or t
EHDX
afterward. G should be kept high
during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a
low onE andG,a low on Wwill disable the outputs
t
WLQZ
after W falls.
DATA RETENTION MODE
Withvalid V
CC
applied, the M48Z30/30Yoperates
as a conventional BYTEWIDE
TM
static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself t
WP
after V
CC
falls below V
PFD
. All outputs
becomehigh impedance,andallinputsaretreated
as ”don’tcare.”
If powerfail detectionoccursduringavalidaccess,
the memory cycle continues to completion. If the
memory cyclefails to terminate within the time t
WP
,
write protection takes place. When Vcc drops be-
low V
SO
, the control circuit switches power to the
internal energy sourcewhich preservesdata.
The internal coin cell will maintain data in the
M48Z30/30Y after the initial applicationof V
CC
for
an accumulated period of at least 10 years when
V
CC
isless thanV
SO
. Assystem powerreturnsand
Vcc rises above V
SO
, the battery is disconnected,
and the power supply is switched to external Vcc.
Writeprotectioncontinuesfort
ER
afterV
CC
reaches
V
PFD
to allow for processor stabilization. After t
ER
,
normal RAM operation can resume.
WRITE MODE
(cont’d)
7/12
M48Z30, M48Z30Y
相關PDF資料 |
PDF描述 |
|---|---|
| M48Z30 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30-100PM1 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30-85PM1 | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30PM | CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30Y | CMOS 32K x 8 ZEROPOWER SRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z30Y-85PM1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z30YPM | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:CMOS 32K x 8 ZEROPOWER SRAM |
| M48Z32V | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM |
| M48Z32V_07 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:3.3V, 256Kbit (32Kbit x 8) ZEROPOWER SRAM |
| M48Z32V-35MT1 | 功能描述:NVRAM 256K (32Kx8) 35ns RoHS:否 制造商:Maxim Integrated 數(shù)據(jù)總線寬度:8 bit 存儲容量:1024 Kbit 組織:128 K x 8 接口類型:Parallel 訪問時間:70 ns 電源電壓-最大:5.5 V 電源電壓-最小:4.5 V 工作電流:85 mA 最大工作溫度:+ 70 C 最小工作溫度:0 C 封裝 / 箱體:EDIP 封裝:Tube |
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