參數(shù)資料
型號(hào): M48Z32V-35MT1TR
廠商: 意法半導(dǎo)體
英文描述: 3.3V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM
中文描述: 3.3伏,256千位32千位× 8 ZEROPOWER的SRAM
文件頁(yè)數(shù): 1/16頁(yè)
文件大?。?/td> 103K
代理商: M48Z32V-35MT1TR
1/16
November 2002
M48Z32V
3.3V, 256 Kbit (32 Kbit x 8) ZEROPOWER
SRAM
FEATURES SUMMARY
I
INTEGRATED, ULTRA LOW POWER SRAM,
and POWER-FAIL CONTROL CIRCUIT
I
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
I
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
I
WRITE PROTECT VOLTAGES:
(V
PFD
= Power-fail Deselect Voltage)
– M48Z32V: 2.7V
V
PFD
3.0V
I
ULTRA-LOW STANDBY CURRENT
Figure 1. Logic Diagram
Figure 2. 44-pin, Hatless SOIC Package
Table 1. Signal Names
AI04787
15
A0-A14
W
DQ0-DQ7
VCC
M48Z32V
G
VSS
8
B +
E
A0-A14
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable Input
G
Output Enable Input
W
WRITE Enable Input
V
CC
Supply Voltage
V
SS
Ground
B +
Positive Battery Pin
NC
Not Connected
44
1
SOH44 (MT)
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