參數(shù)資料
型號(hào): M48Z35AV-70MH6
廠商: 意法半導(dǎo)體
英文描述: 256 Kbit 32Kb x8 ZEROPOWER SRAM
中文描述: 256千位的32KB的SRAM x8 ZEROPOWER
文件頁(yè)數(shù): 1/18頁(yè)
文件大?。?/td> 135K
代理商: M48Z35AV-70MH6
1/18
August 1999
M48Z35
M48Z35Y
256 Kbit (32Kb x8) ZEROPOWER
SRAM
I
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
I
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
I
AUTOMATIC POWER-FAIL CHIP DESELECT
and WRITE PROTECTION
I
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z35: 4.50V
V
PFD
4.75V
– M48Z35Y: 4.20V
V
PFD
4.50V
I
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
I
PACKAGING INCLUDES a 28-LEAD SOIC and
SNAPHAT
TOP (to be Ordered Separately)
I
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
I
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 32K x8 SRAMs
DESCRIPTION
The M48Z35/35Y ZEROPOWER
RAM is a 32
Kbit x8 non-volatile static RAM that integrates
power-fail deselect circuitry and battery control
logic on a single die. The monolithic chip is avail-
able in two special packages to provide a highly in-
tegrated battery backed-up memory solution.
Figure 1. Logic Diagram
AI01616D
15
A0-A14
W
DQ0-DQ7
VCC
M48Z35
M48Z35Y
G
VSS
8
E
Table 1. Signal Names
A0-A14
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
28
1
28
1
SOH28 (MH)
SNAPHAT (SH)
Battery
PCDIP28 (PC)
Battery CAPHAT
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