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參數(shù)資料
| 型號： | M48Z35AV-70MH6TR |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 256 Kbit 32Kb x8 ZEROPOWER SRAM |
| 中文描述： | 256千位的32KB的SRAM x8 ZEROPOWER |
| 文件頁數(shù)： | 4/18頁 |
| 文件大?。?/td> | 135K |
| 代理商： | M48Z35AV-70MH6TR |
M48Z35, M48Z35Y
4/18
The SOIC and battery packages are shipped sep-
arately in plastic anti-static tubes or in Tape & Reel
form.
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z35/35Y also has its own Power-fail De-
tect circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation brought on by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
READ MODE
The M48Z35/35Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
The device architecture allows ripple-through ac-
cess of data from eight of 264,144 locations in the
static storage array. Thus, the unique address
specified by the 15 Address Inputs defines which
one of the 32,768 bytes of data is to be accessed.
Valid data will be available at the Data I/O pins
within Address Access time (t
AVQV
) after the last
address input signal is stable, providing that the E
and G access times are also satisfied. If the E and
G access times are not met, valid data will be
available after the latter of the Chip Enable Access
time (t
ELQV
) or Output Enable Access time
(t
GLQV
).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
ed before t
AVQV
, the data lines will be driven to an
indeterminate state until t
AVQV
. If the Address In-
puts are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (t
AXQX
) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48Z35/35Y is in the Write Mode whenever
W and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of t
EHAX
from Chip Enable or t
WHAX
from Write En-
able prior to the initiation of another read or write
cycle. Data-in must be valid t
DVWH
prior to the end
of write and remain valid for t
WHDX
afterward. G
should be kept high during write cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G, a low on W
will disable the outputs t
WLQZ
after W falls.
Table 4. AC Measurement Conditions
Note that Output Hi-Z is defined as the point where data is no longer
driven.
Input Rise and Fall Times
≤
5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Figure 4. AC Testing Load Circuit
AI03211
CL = 100pF or
5pF
CL includes JIG capacitance
645
DEVICE
UNDER
TEST
1.75V
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| M48Z35AY-70MH1 | 256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AY-70MH1TR | 256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AY-70MH6 | 256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AY-70MH6TR | 256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AY-70PC1 | 256 Kbit 32Kb x8 ZEROPOWER SRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M48Z35AV-70PC1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AV-70PC1TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AV-70PC6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AV-70PC6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 ZEROPOWER SRAM |
| M48Z35AVMH | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:256 Kbit 32Kb x8 ZEROPOWER SRAM |
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