參數(shù)資料
型號(hào): M48Z512A-70CS9
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8 ZEROPOWER SRAM
中文描述: 4兆位的SRAM 512KB的x8 ZEROPOWER
文件頁(yè)數(shù): 7/17頁(yè)
文件大?。?/td> 101K
代理商: M48Z512A-70CS9
7/17
M48Z512A, M48Z512AY
Figure 7. Address Controlled, Read Mode AC Waveforms
Note:
Chip Enable (E) and Output Enable (G) = Low, Write Enable (W) = High.
AI01220
tAXQX
DATA VALID
A0-A18
DQ0-DQ7
tAVAV
tAVQV
Table 9. Read Mode AC Characteristics
(T
A
= 0 to 70
°
C; V
CC
= 4.75V to 5.5V or 4.5V to 5.5V)
Note: 1. C
L
= 100pF.
2. C
L
= 5pF.
Symbol
Parameter
M48Z512A/M48Z512AY
Unit
-70
-85
Min
Max
Min
Max
t
AVAV
Read Cycle Time
70
85
ns
t
AVQV(1)
Address Valid to Output Valid
70
85
ns
t
ELQV(1)
Chip Enable Low to Output Valid
70
85
ns
t
GLQV(1)
Output Enable Low to Output Valid
35
45
ns
t
ELQX(2)
Chip Enable Low to Output Transition
5
5
ns
t
GLQX(2)
Output Enable Low to Output Transition
5
5
ns
t
EHQZ(2)
Chip Enable High to Output Hi-Z
30
35
ns
t
GHQZ(2)
Output Enable High to Output Hi-Z
20
25
ns
t
AXQX(1)
Address Transition to Output Transition
5
5
ns
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M48Z512A-70CS1 4 Mbit 512Kb x8 ZEROPOWER SRAM
M48Z512AY 4 Mbit 512Kb x8 ZEROPOWER SRAM
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