參數(shù)資料
型號: M48Z512AY-70PM9
廠商: 意法半導(dǎo)體
英文描述: 4 Mbit 512Kb x8 ZEROPOWER SRAM
中文描述: 4兆位的SRAM 512KB的x8 ZEROPOWER
文件頁數(shù): 3/17頁
文件大小: 101K
代理商: M48Z512AY-70PM9
3/17
M48Z512A, M48Z512AY
The M48Z512A/512AY also has itsown Power-fail
Detect circuit. Thecontrol circuitry constantlymon-
itors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operation broughton by low V
CC
. As V
CC
falls
below approximately 3V, the control circuitry con-
nects the battery which maintains data until valid
power returns.
The ZEROPOWER RAM replaces industry stan-
dard SRAMs. It provides the nonvolatility of
PROMs without any requirement for special write
Figure 3. Block Diagram
AI02045
INTERNAL
BATTERY
E
VCC
VSS
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
512K x
8
SRAM ARRAY
A0-A18
DQ0-DQ7
W
G
POWER
E
timing or limitations on the number of writes that
can be performed.
The M48Z512A/512AY has itsown Power-fail De-
tect Circuit. The control circuitry constantly moni-
tors the single 5V supply for an out of tolerance
condition. When V
CC
is out of tolerance, the circuit
write protects the SRAM, providing a high degree
of data security in the midst of unpredictable sys-
tem operations brought on by low V
CC
. As V
CC
falls below approximately 3V, the control circuitry
connects thebattery which sustainsdata untilvalid
power returns.
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