參數(shù)資料
型號: M48Z58
廠商: 意法半導(dǎo)體
英文描述: 64 Kbit 8Kb x 8 ZEROPOWER SRAM
中文描述: 64千位的8kB × 8 ZEROPOWER的SRAM
文件頁數(shù): 1/17頁
文件大小: 133K
代理商: M48Z58
M48Z58
M48Z58Y
64 Kbit (8Kb x 8) ZEROPOWER
SRAM
March 1999
1/17
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
PFD
= Power-fail Deselect Voltage):
– M48Z58: 4.50V
V
PFD
4.75V
– M48Z58Y: 4.20V
V
PFD
4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT
TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
The M48Z58/58Y ZEROPOWER
RAM is an 8K x
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
AI01176B
13
A0-A12
W
DQ0-DQ7
VCC
M48Z58
M48Z58Y
G
VSS
8
E
Figure 1. Logic Diagram
A0-A12
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
V
CC
Supply Voltage
V
SS
Ground
Table 1. Signal Names
28
1
PCDIP28 (PC)
Battery CAPHAT
SNAPHAT (SH)
Battery
28
1
SOH28 (MH)
相關(guān)PDF資料
PDF描述
M48Z58MH 64 Kbit 8Kb x 8 ZEROPOWER SRAM
M48Z58PC 64 Kbit 8Kb x 8 ZEROPOWER SRAM
M48Z58SH 64 Kbit 8Kb x 8 ZEROPOWER SRAM
M48Z58Y 64 Kbit 8Kb x 8 ZEROPOWER SRAM
M48Z58-70MH1 64 Kbit 8Kb x 8 ZEROPOWER SRAM
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