參數(shù)資料
型號: M4A5-96/48-10VC
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 16/62頁
文件大?。?/td> 0K
描述: IC CPLD ISP 4A 96MC 100TQFP
標(biāo)準(zhǔn)包裝: 90
系列: ispMACH® 4A
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
宏單元數(shù): 96
輸入/輸出數(shù): 48
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 托盤
ispMACH 4A Family
23
MACROCELL
M0
C0
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
B
89
M0
M4A(3, 5)-64/32
M4A3-64/64
M4A(3, 5)-96/48
M4A(3, 5)-128/64
A
B
16
17
M4(3, 5)-192/96
M4(3, 5)-256/128
M4A3-384
M4A3-512
18
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
O0
O1
O2
O3
O4
O5
O6
O7
M15
CLK0
CLK1
CLK2
CLK3
I/O
CELL
I/O0
CLOCK
GENERATOR
MACROCELL
CENTRAL
SWITCH
MA
TRIX
MACROCELL
24
A
0
4
16
C1
C2
I/O
CELL
I/O1
C3
C4
I/O
CELL
I/O2
C5
C6
I/O
CELL
I/O3
C7
C8
I/O
CELL
I/O4
C9
C10
I/O
CELL
I/O5
C11
C12
I/O
CELL
I/O6
C13
C14
I/O
CELL
INPUT SWITCH
MATRIX
I/O7
C15
LOGIC
ALLOCA
T
O
R
OUTPUT
SWITCH
MA
TRIX
Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio
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