參數(shù)資料
型號(hào)： M5-128/68-7VC/1
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 42/42頁(yè)
文件大小： 0K
描述： IC CPLD ISP 128MC 68IO 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： MACH® 5
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 7.5ns
電壓電源 - 內(nèi)部： 4.75 V ~ 5.25 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 68
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
MACH 5 Family
9
MACH 5 TIMING MODEL
The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5 device,
and at the same time, be easy to understand. This model accurately describes all combinatorial and registered
paths through the device, making a distinction between
internal feedback and external feedback. A signal
uses internal feedback when it is fed back into the switch matrix or block without having to go through the
output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back
into the switch matrix after having gone through the output buffer, it is using external feedback.
The parameter, tBUF, is defined as the time it takes to go through the output buffer to the I/O pad. If a signal
goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an “i”. By
adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A
diagram representing the modularized MACH 5 timing model is shown in Figure 7. Refer to the Technical
Note entitled MACH 5 Timing and High Speed Design for a more detailed discussion about the timing parameters.
INPUT REG/
INPUT LATCH
tSIR (S/A)
tHIR (S/A)
tSIL
tHIL
tSRR
tCES
tCEH
tCO (S/A) i
tPDILi
tGOAi
tSRi
tBLK
tSEG
CE
SR
(External Feedback)
(Internal Feedback)
Q
tS (S/A)
tH (S/A)
tSAL
tHAL
tSRR
tCES
tCEH
tPDi
tCO (S/A) i
tPDLi
tGOAi
tSRi
COMB/DFF/
LATCH
CE
SR
tPL1
tPL2
tPL3
IN
OUT
tPT
tEA
tER
tBUF
tSLW
PIN CLK
Q
20446G-014
Figure 7. MACH 5 Timing Model
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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