1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices. GENERAL DESCRIPTION The MACH
參數資料
型號： M5-192/120-5YC/1
廠商： Lattice Semiconductor Corporation
文件頁數： 12/42頁
文件大?。?/td> 0K
描述： IC CPLD ISP 192MC 120IO 160PQFP
標準包裝： 24
系列： MACH® 5
可編程類型： 系統(tǒng)內可編程
最大延遲時間 tpd(1)： 5.5ns
電壓電源 - 內部： 4.75 V ~ 5.25 V
宏單元數： 192
輸入/輸出數： 120
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 160-BQFP
供應商設備封裝： 160-PQFP（28x28）
包裝： 托盤
2
MACH 5 Family
Note:
1.
“M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.
GENERAL DESCRIPTION
The MACH 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic
Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low
power, and supports additional features such as in-system programmability, Boundary Scan testability, and
advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx)
operation.
Manufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies,
MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-
ns devices are compliant with the PCI Local Bus Specification.
Table 1. MACH 5 Device Features 1
Feature
M5-128/1
M5LV-128
M5-192/1
M5-256/1
M5LV-256
M5-320
M5LV-320
M5-384
M5LV-384
M5-512
M5LV-512
Supply Voltage (V)
5
3.3
5
3.3
5
3.3
5
3.3
5
3.3
Macrocells
128
192
256
320
384
512
Maximum User I/O Pins
120
160
192
160
256
tPD (ns)
5.5
6.5
tSS (ns)
3.0
tCOS (ns)
4.5
5.0
fCNT (MHz)
182
167
Typical Static Power (mA)
35
45
55
70
75
100
IEEE 1149.1 Boundary Scan Compliant
Yes
PCI-Compliant
Yes
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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