1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site. 2.
參數(shù)資料
型號(hào): M5-384/160-10YC
廠商: Lattice Semiconductor Corporation
文件頁(yè)數(shù): 18/42頁(yè)
文件大小: 0K
描述: IC CPLD ISP 384MC 160IO 208PQFP
標(biāo)準(zhǔn)包裝: 24
系列: MACH® 5
可編程類型: 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1): 10.0ns
電壓電源 - 內(nèi)部: 4.75 V ~ 5.25 V
宏單元數(shù): 384
輸入/輸出數(shù): 160
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
MACH 5 Family
25
Notes:
1.
See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site.
2.
Numbers in parentheses are for M5-128, M5-192, M5-256.
3.
If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (fMAX/2).
Frequency:
fMAX
External feedback, PAL block level. Min
of 1/(tWLS + tWHS) or 1/(tSS + tCOS)
133
125
100
83.3
71.4
55.6
45.5
MHz
Internal feedback, PAL block level. Min
of 1/(tWLS + tWHS) or 1/(tSS +tCOSi)
182
167
125
100
83.3
62.5
50.0
MHz
No feedback PAL block level. Min of
1/(tWLS + tWHS) or 1/(tSS + tHS)
200
167
125
100
83.3
MHz
fMAXA
External feedback, PAL block level. Min
of 1/(tWLA + tWHA) or 1/(tSA + tCOA)
91
71.4
58.8
47.6
41.7
35.7
MHz
Internal feedback, PAL block level. Min
of 1/(tWLA + tWHA) or 1/(tSA +tCOAi)
111
83.3
66.7
52.6
45.5
38.5
MHz
No feedback, PAL block level. Min of
1/(tWLA + tWHA) or 1/(tSA + tHA)
167
125
100
83.3
71.4
62.5
MHz
fMAXI
Maximum input register frequency
1/(tSIRS+tHIRS) or 1/(2 x tWICW)
167
125
100
83.3
71.4
62.5
MHz
M5(LV) TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED)
-5
-6
-7
-10
-12
-15
-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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