- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19624 > M5-384/160-15YI (Lattice Semiconductor Corporation)IC CPLD ISP 384MC 160IO 208PQFP PDF資料下載
參數(shù)資料
| 型號： | M5-384/160-15YI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 34/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD ISP 384MC 160IO 208PQFP |
| 標準包裝： | 24 |
| 系列： | MACH® 5 |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 15.0ns |
| 電壓電源 - 內部： | 4.5 V ~ 5.5 V |
| 宏單元數(shù)： | 384 |
| 輸入/輸出數(shù)： | 160 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
4
MACH 5 Family
and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test
Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block
interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the
segments together. The only logic difference between any two MACH 5 devices is the number of segments.
Therefore, once a designer is familiar with one device, consistent performance can be expected across the
entire family. All devices have four clock pins available which can also be used as logic inputs.
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an
independent PAL device, it has superior control and logic generation capabilities.
◆ I/O cells
◆ Product-term array and Logic Allocator
◆ Macrocells
◆ Register control generator
◆ Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local feedback.
If the I/O is used in another PAL block, the
interconnect feeder assigns a block interconnect line to that
signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide
connections between any two signals in a device. The
block feeder assigns block interconnect lines and local
feedback lines to the PAL block inputs.
Block
Interconnect
4
CLK
Block:
16 MCs
Segment:
4 Blocks
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關PDF資料 |
PDF描述 |
|---|---|
| V150A48E400BF2 | CONVERTER MOD DC/DC 48V 400W |
| RCM06DRST | CONN EDGECARD 12POS DIP .156 SLD |
| ABC26DRAS-S734 | CONN EDGECARD 52POS .100 R/A PCB |
| DEBB33A472KA3B | CAP CER 4700PF 1KV 10% RADIAL |
| VI-BWK-CW-B1 | CONVERTER MOD DC/DC 40V 100W |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5386 | 制造商:Tamura Corporation of America 功能描述: |
| M-538CT | 制造商:NEC 制造商全稱:NEC 功能描述:DC Line Fileters |
| M539 | 制造商:MA-COM 制造商全稱:M/A-COM Technology Solutions, Inc. 功能描述:Drivers for GaAs FET MMIC Switches and Digital Attenuators |
| M5390 NC001 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 18AWG NC 1000' |
| M5390 NC002 | 制造商:Alpha Wire Company 功能描述:CBL 2COND 18AWG NC 500' |
發(fā)布緊急采購，3分鐘左右您將得到回復。