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參數(shù)資料
| 型號： | M50FLW080ANB5P |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| 中文描述： | 8兆位（13 × 64KB之座3 × 16 × 4KB的部門），3V電源固件集線器/低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 20/64頁 |
| 文件大?。?/td> | 341K |
| 代理商： | M50FLW080ANB5P |
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Bus operations
M50FLW080A, M50FLW080B
20/64
FWH Bus Read field definitions
Figure 6.
FWH Bus Read waveforms
Table 6.
Clock
Cycle
Number
Clock
Cycle
Count
Field
FWH0-
FWH3
Memory
I/O
Description
1
1
START
1101b
I
On the rising edge of CLK with FWH4 Low, the contents of FWH0-
FWH3 indicate the start of a FWH Read cycle.
2
1
IDSEL
XXXX
I
Indicates which FWH Flash Memory is selected. The value on
FWH0-FWH3 is compared to the IDSEL strapping on the FWH
Flash Memory pins to select which FWH Flash Memory is being
addressed.
3-9
7
ADDR
XXXX
I
A 28-bit address is transferred, with the most significant nibble
first. For the multi-byte read operation, the least significant bits
(MSIZE of them) are treated as Don't Care, and the read operation
is started with each of these bits reset to 0. Address lines A20-21
and A23-27 are treated as Don’t Care during a normal memory
array access, with A22=1, but are taken into account for a register
access, with A22=0. (See
Table 15
)
10
1
MSIZE
XXXX
I
This one clock cycle is driven by the host to determine the number
of Bytes that will be transferred. M50FLW080 supports: single
Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer
(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).
11
1
TAR
1111b
I
The host drives FWH0-FWH3 to 1111b to indicate a turnaround
cycle.
12
1
TAR
1111b
(float)
O
The FWH Flash Memory takes control of FWH0-FWH3 during this
cycle.
13-14
2
WSYNC 0101b
O
The FWH Flash Memory drives FWH0-FWH3 to 0101b (short
wait-sync) for two clock cycles, indicating that the data is not yet
available. Two wait-states are always included.
15
1
RSYNC
0000b
O
The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating
that data will be available during the next clock cycle.
16-17
M=2n
DATA
XXXX
O
Data transfer is two CLK cycles, starting with the least significant
nibble. If multi-Byte read operation is enabled, repeat cycle-16 and
cycle-17
n
times, where
n = 2
MSIZE
.
previous
+1
1
TAR
1111b
O
The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate
a turnaround cycle.
previous
+1
1
TAR
1111b
(float)
N/A
The FWH Flash Memory floats its outputs, the host takes control
of FWH0-FWH3.
AI08433B
CLK
FWH4
FWH0-FWH3
Number of
clock cycles
START
IDSEL
ADDR
MSIZE
TAR
SYNC
DATA
TAR
1
1
7
1
2
3
M
2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50FLW080ANB5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080ANB5TG | 功能描述:閃存 8 Mbit RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50FLW080ANB5TP | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8 Mbit (13 x 64KByte Blocks + 3 x 16 x 4KByte Sectors), 3V Supply Firmware Hub / Low Pin Count Flash Memory |
| M50FLW080AXW21/I | 功能描述:閃存 8-bit MCU 閃存 RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50FLW080AYW21 | 功能描述:閃存 SERIAL FLASH RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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