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參數(shù)資料
| 型號(hào)： | M50LPW002 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 2兆位的256Kb × 8，啟動(dòng)塊3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 4/39頁 |
| 文件大?。?/td> | 258K |
| 代理商： | M50LPW002 |
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M50LPW002
4/39
SUMMARY DESCRIPTION
The M50LPW002 is a 2 Mbit (256Kb x8) non-vola-
tile memory that can be read, erased and repro-
grammed. These operations can be performed
using a single low voltage (3.0 to 3.6V) supply. For
fast programming and fast erasing in production
lines an optional 12V power supply can be used to
reduce the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually to prevent accidental Pro-
gram or Erase commands from modifying the
memory. Program and Erase commands are writ-
ten to the Command Interface of the memory. An
on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents. The end
of a program or erase operation can be detected
and any error conditions identified. The command
set required to control the memory is consistent
with JEDEC standards.
The device features an asymmetrical blocked ar-
chitecture. The device has an array of 7 blocks:
I
1 Boot Block of 16 KByte
I
2 Parameter Blocks of 8 KByte each
I
1 Main Block of 32 KByte
I
3 Main Blocks of 64 KByte each
Two different bus interfaces are supported by the
memory. The primary interface is the Low Pin
Count (or LPC) Standard Interface. This has been
designed to remove the need for the ISA bus in
current PC Chipsets; the M50LPW002 acts as the
PC BIOS on the Low Pin Count bus for these PC
Chipsets.
The secondary interface, the Address/Address
Multiplexed (or A/A Mux) Interface, is designed to
be compatible with current Flash Programmers for
production line programming prior to fitting to a PC
Motherboard.
The memory is delivered with all the bits erased
(set to 1).
Figure 2. PLCC Connections
Note: Pins 27 and 28 are not internally connected.
AI05744
G
NC
VSS
VCC
INIT
LFRAME
RFU
R
17
ID1
ID0
LAD0
L
L
L
R
GPI1
GPI0
WP
TBL
ID3
ID2
9
C
1
R
NC
G
RFU
32
V
V
M50LPW002
G
IC (VIL)
R
25
V
A1
A0
DQ0
A7
A6
A5
A4
A3
A2
A
R
R
A
V
V
A
NC
VSS
VCC
G
W
RB
NC
DQ7
IC (VIH)
D
D
D
D
D
D
V
A/A Mux
A/A Mux
A/A Mux
A/A Mux
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50LPW002K | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K1T | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K5T | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012 | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012K | 2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW002K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW002K5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
| M50LPW012K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:2 Mbit 256Kb x8, Boot Block 3V Supply Low Pin Count Flash Memory |
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