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參數(shù)資料
| 型號： | M50LPW040 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| 中文描述： | 4兆位512KB的× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 272K |
| 代理商： | M50LPW040 |
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M50LPW040
4/36
Low Pin Count (LPC) Signal Descriptions
For the Low Pin Count (LPC) Interface see Figure
1, Logic Diagram, and Table 1, Signal Names.
Input/Output Communications (LAD0-LAD3).
All
Input and Output Communication with the memory
take place on these pins. Addresses and Data for
Bus Read and Bus Write operations are encoded
on these pins.
Input Communication Frame (LFRAME).
The
Input Communication Frame (LFRAME) signals
the start of a bus operation. When Input Commu-
nication Frame is Low, V
IL
, on the rising edge of
the Clock a new bus operation is initiated. If Input
Communication Frame is Low, V
IL
, during a bus
operation then the operation is aborted. When In-
put Communication Frame is High, V
IH
, the cur-
rent bus operation is proceeding or the bus is idle.
Identification Inputs (ID0-ID2).
The Identification
Inputs (ID0-ID2) allow to address up to 8
memories on a bus. The value on addresses A19-
A21 is compared to the hardware strapping on the
ID0-ID2 pins to select which memory is being
addressed. For an address bit to be ‘1’ the
correspondent ID pin can be left floating or driven
Low, V
IL
; an internal pull-down resistor is included
with a value of R
IL
. For an address bit to be ‘0’ the
correspondent ID pin must be driven High, V
IH
;
there will be a leakage current of I
LI2
through each
pin when pulled to V
IH
; see Table 20.
By convention the boot memory must have ID0-
ID2 pins left floating or driven Low, V
IL
and a ‘111’
value on A19-A21 and all additional memories
take sequential ID0-ID2 configuration, as shown in
Table 2.
General Purpose Inputs (GPI0-GPI4).
The Gener-
al Purpose Inputs can be used as digital inputs for
the CPU to read. The General Purpose Input Reg-
ister holds the values on these pins. The pins must
have stable data from before the start of the cycle
that reads the General Purpose Input Register un-
til after the cycle is complete. These pins must not
be left to float, they should be driven Low, V
IL,
or
High, V
IH
.
Interface Configuration (IC).
The Interface Con-
figuration input selects whether the Low Pin Count
(LPC) or the Address/Address Multiplexed (A/A
Mux) Interface is used. The chosen interface must
be selected before power-up or during a Reset
and, thereafter, cannot be changed. The state of
the Interface Configuration, IC, should not be
changed during operation.
To select the Low Pin Count (LPC) Interface the
Interface Configuration pin should be left to float or
driven Low, V
IL
; to select the Address/Address
Multiplexed (A/A Mux) Interface the pin should be
driven High, V
IH
. An internal pull-down resistor is
included with a value of R
IL
; there will be a leakage
current of I
LI2
through each pin when pulled to V
IH
;
see Table 20.
Interface Reset (RP).
The Interface Reset (RP)
input is used to reset the memory. When Interface
Reset (RP) is set Low, V
IL
, the memory is in Reset
mode: the outputs are put to high impedance and
the current consumption is minimized. When RP is
set High, V
IH
, the memory is in normal operation.
After exiting Reset mode, the memory enters
Read mode.
CPU Reset (INIT).
The CPU Reset, INIT, pin is
used to Reset the memory when the CPU is reset.
It behaves identically to Interface Reset, RP, and
the internal Reset line is the logical OR (electrical
AND) of RP and INIT.
Clock (CLK).
The Clock, CLK, input is used to
clock the signals in and out of the Input/Output
Communication Pins, LAD0-LAD3. The Clock
conforms to the PCI specification.
Table 2. Memory Identification Input Configuration
Memory Number
ID2
ID1
ID0
A21
A20
A19
1 (Boot)
V
IL
or floating
V
IL
or floating
V
IL
or floating
1
1
1
2
V
IL
or floating
V
IL
or floating
V
IH
1
1
0
3
V
IL
or floating
V
IH
V
IL
or floating
1
0
1
4
V
IL
or floating
V
IH
V
IH
1
0
0
5
V
IH
V
IL
or floating
V
IL
or floating
0
1
1
6
V
IH
V
IL
or floating
V
IH
0
1
0
7
V
IH
V
IH
V
IL
or floating
0
0
1
8
V
IH
V
IH
V
IH
0
0
0
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M50LPW040K | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040K1T | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040K5T | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040N | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040N1T | 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M50LPW040K | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040K1 | 功能描述:閃存 3.6V 4M (512Kx8) RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲類型:Flash 存儲容量:2 MB 結(jié)構(gòu):256 K x 8 定時類型: 接口類型:SPI 訪問時間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
| M50LPW040K1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040K5T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
| M50LPW040N | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory |
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