參數(shù)資料
型號(hào)： M50LPW041K
廠商： 意法半導(dǎo)體
英文描述： 4 Mbit 512Kb x8, Uniform Block 3V Supply Low Pin Count Flash Memory
中文描述： 4兆位512KB的× 8，統(tǒng)一座3V電源低引腳數(shù)快閃記憶體
文件頁數(shù)： 12/37頁
文件大小： 268K
代理商： M50LPW041K
M50LPW041
12/37
Block Erase Command.
The Block Erase com-
mand can be used to erase a block. Two Bus Write
operations are required to issue the command; the
second Bus Write cycle latches the block address
in the internal state machine and starts the Pro-
gram/Erase Controller. Once the command is is-
sued subsequent Bus Read operations read the
Status Register. See the section on the Status
Register for details on the definitions of the Status
Register bits.
If the block is protected then the Block Erase
operation will abort, the data in the block will not be
changed and the Status Register will output the
error.
During the Block Erase operation the memory will
only accept the Read Status Register command
and the Program/Erase Suspend command. All
other commands will be ignored. Typical Block
Erase times are given in Table 13.
The Block Erase command sets all of the bits in
the block to ‘1’. All previous data in the block is
lost.
See Figure 18, Block Erase Flowchart and Pseudo
Code
,
for a suggested flowchart on using the
Block Erase command.
Clear Status Register Command.
The Clear Sta-
tus Register command can be used to reset bits 1,
3, 4 and 5 in the Status Register to ‘0’. One Bus
Write is required to issue the Clear Status Register
command. Once the command is issued the mem-
ory returns to its previous mode, subsequent Bus
Read operations continue to output the same data.
The bits in the Status Register are sticky and do
not automatically return to ‘0’ when a new Program
or Erase command is issued. If an error occurs
then it is essential to clear any error bits in the Sta-
tus Register by issuing the Clear Status Register
command before attempting a new Program or
Erase command.
Program/Erase Suspend Command.
The
gram/Erase Suspend command can be used to
pause a Program or Block Erase operation. One
Bus Write cycle is required to issue the Program/
Erase Suspend command and pause the Pro-
gram/Erase Controller. Once the command is is-
sued it is necessary to poll the Program/Erase
Controller Status bit to find out when the Program/
Erase Controller has paused; no other commands
will be accepted until the Program/Erase Control-
ler has paused. After the Program/Erase Control-
ler has paused, the memory will continue to output
the Status Register until another command is is-
sued.
During the polling period between issuing the
Program/Erase Suspend command and the
Program/Erase Controller pausing it is possible for
the operation to complete. Once Program/Erase
Pro-
Controller Status bit indicates that the Program/
Erase Controller is no longer active, the Program
Suspend Status bit or the Erase Suspend Status
bit can be used to determine if the operation has
completed or is suspended. For timing on the
delay between issuing the Program/Erase
Suspend command and the Program/Erase
Controller pausing see Table 13.
During Program/Erase Suspend the Read
Memory Array, Read Status Register, Read
Electronic Signature and Program/Erase Resume
commands will be accepted by the Command
Interface. Additionally, if the suspended operation
was Block Erase then the Program command will
also be accepted; only the blocks not being erased
may be read or programmed correctly.
See Figures 16, Program Suspend & Resume
Flowchart and Pseudo Code, and 19, Erase
Suspend & Resume Flowchart and Pseudo Code,
for suggested flowcharts on using the Program/
Erase Suspend command.
Program/Erase Resume Command.
The
gram/Erase Resume command can be used to re-
start the Program/Erase Controller after a
Program/Erase Suspend has paused it. One Bus
Write cycle is required to issue the Program/Erase
Resume command. Once the command is issued
subsequent Bus Read operations read the Status
Register.
Pro-
STATUS REGISTER
The Status Register provides information on the
current or previous Program or Erase operation.
Different bits in the Status Register convey
different information and errors on the operation.
To read the Status Register the Read Status
Register command can be issued. The Status
Register is automatically read after Program,
Erase and Program/Erase Resume commands
are issued. The Status Register can be read from
any address.
The Status Register bits are summarized in Table
14, Status Register Bits. Refer to Table 14 in con-
junction with the text descriptions below.
Program/Erase Controller Status (Bit 7).
The Pro-
gram/Erase Controller Status bit indicates whether
the Program/Erase Controller is active or inactive.
When the Program/Erase Controller Status bit is
Table 11. Read Electronic Signature
Note: For A19 value, see Table 2.
Code
Address
Data
Manufacturer Code
00000h
20h
Device Code
00001h
3Ch
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