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M50LPW080
Figure 2. Logic Diagram (LPC Interface)
Figure 3. Logic Diagram (A/A Mux Interface)
Table 1. Signal Names (LPC Interface)
Table 2. Signal Names (A/A Mux Interface)
AI04426
2
LFRAME
LAD0-
LAD3
VCC
M50LPW080
CLK
VSS
4
IC
RP
TBL
5
INIT
WP
ID0-ID1
GPI0-
GPI4
VPP
AI04427
11
RC
DQ0-DQ7
VCC
M50LPW080
IC
VSS
8
G
W
RB
RP
A0-A10
VPP
LAD0-LAD3
Input/Output Communications
LFRAME
Input Communication Frame
ID0-ID1
Identification Inputs
GPI0-GPI4
General Purpose Inputs
IC
Interface Configuration
RP
Interface Reset
INIT
CPU Reset
CLK
Clock
TBL
Top Block Lock
WP
Write Protect
RFU
Reserved for Future Use. Leave
disconnected
V
CC
Supply Voltage
V
PP
Optional Supply Voltage for Fast
Erase Operations
V
SS
Ground
NC
Not Connected Internally
IC
Interface Configuration
A0-A10
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
G
Output Enable
W
Write Enable
RC
Row/Column Address Select
RB
Ready/Busy Output
RP
Interface Reset
V
CC
Supply Voltage
V
PP
Optional Supply Voltage for Fast
Program and Fast Erase Operations
V
SS
Ground
NC
Not Connected Internally