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參數(shù)資料
| 型號： | M52S32162A-7.5BG |
| 廠商： | ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 1M x 16Bit x 2Banks Synchronous DRAM |
| 中文描述： | 2M X 16 SYNCHRONOUS DRAM, 7 ns, PBGA54 |
| 封裝： | 8 X 8 MM, LEAD FREE, VFBGA-54 |
| 文件頁數(shù)： | 6/30頁 |
| 文件大小： | 787K |
| 代理商： | M52S32162A-7.5BG |
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ES MT
AC OPERATING TEST CONDITIONS
(V
DD
=2.5V
±
0.2V,T
A
= 0° ~ 70° )
M52S32162A
Elite Semiconductor Memory Technology Inc.
Publication Date
:
Apr. 2007
Revision
:
1.2
6/30
Parameter
Value
Unit
V
V
ns
V
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
0.9 x V
DDQ
/ 0.2
0.5 x V
DDQ
tr / tf = 1 / 1
0.5 x V
DDQ
See Fig.2
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
-7.5
-10
Unit
Note
Row active to row active delay
t
RRD
(min)
15
20
ns
1
RAS to CAS delay
t
RCD
(min)
22.5
30
ns
1
Row precharge time
t
RP
(min)
22.5
30
ns
1
t
RAS
(min)
45
50
ns
1
Row active time
t
RAS
(max)
100
us
Row cycle time
t
RC
(min)
67.5
90
ns
1
Last data in to new col. Address delay
t
CDL
(min)
1
CLK
2
Last data in to row precharge
t
RDL
(min)
2
CLK
2
Last data in to burst stop
t
BDL
(min)
1
CLK
2
Col. Address to col. Address delay
t
CCD
(min)
1
CLK
3
CAS latency=3
2
Number of valid output data
CAS latency=2
1
ea
4
Note:
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
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