參數(shù)資料
型號: M54HC160
廠商: 意法半導(dǎo)體
元件分類: 通用總線功能
英文描述: Synchronous Presettable 4-Bit Counter(同步可復(fù)位4位計(jì)數(shù)器)
中文描述: 同步可預(yù)置4位計(jì)數(shù)器(同步可復(fù)位4位計(jì)數(shù)器)
文件頁數(shù): 1/16頁
文件大?。?/td> 331K
代理商: M54HC160
M54/74HC160/161
M54/74HC162/163
April1993
SYNCHRONOUS PRESETTABLE 4-BIT COUNTER
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT 25
°
C
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
.
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO6 V
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS160
163
B1R
(Plastic Package)
ORDER CODES :
M54HCXXXF1R
M74HCXXXB1R
M74HCXXXM1R
M74HCXXXC1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Inter-
nal Con-
DESCRIPTION
M54/74HC160 Decade, Asynchronous Clear
M54/74HC161 Binary, Asynchronous Clear
M54/74HC162 Decade, Synchronous Clear
M54/74HC163 Binary, Synchronous Clear
The M54/74HC160, 161, 162 and 163 are high
speed CMOS SYNCHRONOUS PRESETTABLE
COUNTERS fabricated with silicon gate C
2
MOS
technology.
They have the same the high speed operation simi-
lar to equivalent LSTTL while maintaining the
CMOS low powerdissipation.
The M54/74HC160/162 are BCD Decade counters
and theM54/74HC161/163 are4 bitbinary counter-
s.
The CLOCK input is active on the rising edge. Both
LOADand CLEAR inputs are active Low.
Presetting of all four IC’s is synchronous on the ris-
ing edge of the CLOCK.
The function on the M54/74HC162/163 is syn-
chronous to CLOCK, while the M54/74HC160/161
counters are cleared asynchronously.
Two enable inputs(TE and PE) and CARRYoutput
are provided to enable easy cascading of counters,
which facilities easy implementation
counters without using external gates.
All inputs are equipped with protection circuits
against static discharge and transient excess volt-
age.
.
HIGH SPEED
f
MAX
= 63 MHz (TYP.) AT V
CC
= 5 V
of N-bit
1/16
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