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參數(shù)資料
| 型號(hào)： | M54HCT137F1R |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Low-Voltage Adjustable Precision Shunt Regulator 5-SOT-23 -40 to 85 |
| 中文描述： | 3至8線譯碼器/鎖存器反相 |
| 文件頁數(shù)： | 1/12頁 |
| 文件大?。?/td> | 260K |
| 代理商： | M54HCT137F1R |
M54HCT137
M74HCT137
February 1993
3 TO 8 LINE DECODER/LATCH (INVERTING)
.
LOWPOWER DISSIPATION
I
CC
= 4
μ
A(MAX.) AT T
A
= 25
°
C
.
COMPATIBLE WITHTTL OUTPUTS
V
IH
= 2V (MIN.) V
IL
= 0.8V (MAX)
.
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.
SYMMETRICAL OUTPUT IMPEDANCE
IOH
= I
OL
= 4 mA(MIN.)
.
BALANCEDPROPAGATION DELAYS
t
PLH
= t
PHL
.
PIN ANDFUNCTION COMPATIBLE
WITH 54/74LS137
B1R
(Plastic Package)
ORDER CODES :
M54HCT137F1R
M74HCT137B1R
M74HCT137M1R
M74HCT137C1R
F1R
(CeramicPackage)
M1R
(MicroPackage)
C1R
(Chip Carrier)
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
DESCRIPTION
TheM54/74HCT137isahighspeed CMOS3TO8LINE
DECODER/LATCH (INVERTING) fabricated in silicon
gateC
2
MOStechnology.Ithasthesamehighspeedper-
formanceofLSTTLcombinedwithtrueCMOSlowpower
consumption. Thisdeviceisa 3to8linedecoder withlat-
chesonthethreeaddressinputs.WhenGLgoesfromlow
tohigh,theaddress presentattheselectinputs(A,Band
C)isstoredinthelatches.AslongasGLremains high no
address changes willbe recognized. Outputenable pins
G1and G2,control thestateoftheoutputsindependently
oftheselectorlatch-enable inputs.Alltheoutputsarehigh
unless G1 is high and G2 is low. The HC137 is ideally
suited for the implementation of glitch-free decoders in
stored-address applications in bus oriented systems.All
inputs are equipped withprotection circuits against static
discharge and transient excess voltage.This integrated
circuit has input and output characteristics that are fully
compatible with54/74 LSTTLlogic families.M54/74HCT
devicesaredesignedtodirectlyinterfaceHSC
2
MOSsys-
temswithTTLandNMOScomponents.Theyarealso
plug in replacements for LSTTL devices giving a re-
duction of power consumption.
.
HIGH SPEED
t
PD
= 17 ns(TYP.) AT V
CC
= 5 V
1/12
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