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參數(shù)資料
| 型號(hào)： | M58LW064D110ZA |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| 中文描述： | 64兆位（和8Mb × 8，4Mb的x16插槽，統(tǒng)一座）3V電源快閃記憶體 |
| 文件頁數(shù)： | 12/51頁 |
| 文件大?。?/td> | 349K |
| 代理商： | M58LW064D110ZA |
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M58LW064D
12/51
BUS OPERATIONS
There are 6 bus operations that control the mem-
ory. Each of these is described in this section, see
Tables 3, Bus Operations, for a summary.
On Power-up or after a Hardware Reset the mem-
ory defaults to Read Array mode (Page Read).
Typically glitches of less than 5ns on Chip Enable
or Write Enable are ignored by the memory and do
not affect bus operations.
Bus Read.
Bus Read operations read from the
memory cells, or specific registers (Electronic Sig-
nature, Status Register, CFI and Block Protection
Status) in the Command Interface.
A valid bus operation involves setting the desired
address on the Address inputs, enabling the de-
vice (refer to Table 2, Device Enable), applying a
Low signal, V
IL
, to Output Enable and keeping
Write Enable High, V
IH
.
The Data Inputs/Outputs will output the value, see
Figure 9, Bus Read AC Waveforms, and Table 15,
Bus Read AC Characteristics, for details of when
the output becomes valid.
Page Read.
Page Read operations are used to
read from several addresses within the same
memory page.
Each memory page is a 4 Words or 8 Bytes and
has the same A3-A22. In x8 mode only A0, A1 and
A2 may change, in x16 mode only A1 and A2 may
change.
Valid bus operations are the same as Bus Read
operations but with different timings. The first read
operation within the page has identical timings,
subsequent reads within the same page have
much shorter access times. If the page changes
then the normal, longer timings apply again. See
Figure 10, Page Read AC Waveforms and Table
16, Page Read AC Characteristics for details on
when the outputs become valid.
Bus Write.
Bus Write operations write to the
Command Interface in order to send commands to
the memory or to latch addresses and input data
to program.
A valid Asynchronous Bus Write operation begins
by setting the desired address on the Address In-
puts and enabling the device (refer to Chip Enable
section).
The Address Inputs are latched by the Command
Interface on the rising edge of Write Enable or the
first edge of E0, E1 or E2 that disables the device
(refer to Table 2, Device Enable). The Data Input/
Outputs are latched by the Command Interface on
the rising edge of Write Enable or the first edge of
E0, E1 or E2 that disable the device whichever oc-
curs first .
Output Enable must remain High, V
IH
, during the
whole Bus Write operation. See Figures 11, and
12, Write AC Waveforms, and Tables 17 and 18,
Write and Chip Enable Controlled Write AC Char-
acteristics, for details of the timing requirements.
Output Disable.
The Data Inputs/Outputs are in
the high impedance state when the Output Enable
is High.
Standby.
When Chip Enable is High, V
IH
, the
memory enters Standby mode and the Data In-
puts/Outputs pins are placed in the high imped-
ance state regardless of Output Enable or Write
Enable. The Supply Current is reduced to the
Standby Supply Current, I
DD1
.
During Program or Erase operations the memory
will continue to use the Program/Erase Supply
Current, I
DD3
, for Program or Erase operations un-
til the operation completes.
Automatic Low Power.
If there is no change in
the state of the bus for a short period of time during
Asynchronous Bus Read operations the memory
enters Auto Low Power mode where the internal
Supply Current is reduced to the Auto-Standby
Supply Current, I
DD5
. The Data Inputs/Outputs will
still output data if a Bus Read operation is in
progress.
Automatic Low Power is only available in Asyn-
chronous Read modes.
Power-Down.
The memory is in Power-Down
mode when Reset/Power-Down, RP, is Low. The
power consumption is reduced to the Power-Down
level, I
DD2
, and the outputs are high impedance,
independent of Chip Enable, Output Enable or
Write Enable.
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| M58LW064D110N1F | 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| M58LW064D110N1T | 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| M58LW064D110N6 | 64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M58LW064D110ZA1 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| M58LW064D110ZA1E | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| M58LW064D110ZA1F | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| M58LW064D110ZA1T | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:64 Mbit (8Mb x8, 4Mb x16, Uniform Block) 3V Supply Flash Memory |
| M58LW064D110ZA6 | 功能描述:閃存 8Mx8 or 4Mx16 110ns RoHS:否 制造商:ON Semiconductor 數(shù)據(jù)總線寬度:1 bit 存儲(chǔ)類型:Flash 存儲(chǔ)容量:2 MB 結(jié)構(gòu):256 K x 8 定時(shí)類型: 接口類型:SPI 訪問時(shí)間: 電源電壓-最大:3.6 V 電源電壓-最小:2.3 V 最大工作電流:15 mA 工作溫度:- 40 C to + 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體: 封裝:Reel |
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