參數(shù)資料
型號(hào)： M58LW128B150ZA1E
廠商： 意法半導(dǎo)體
英文描述： 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
中文描述： 128兆位和8Mb x16或4Mb的X32號(hào)，統(tǒng)一座，突發(fā)3V電源閃存
文件頁(yè)數(shù)： 16/65頁(yè)
文件大?。?/td> 932K
代理商： M58LW128B150ZA1E
M58LW128A, M58LW128B
16/65
Synchronous Bus Operations
For synchronous bus operations refer to Table 3
together with the text below.
Synchronous Burst Read.
Synchronous Burst
Read operations are used to read from the memo-
ry at specific times synchronized to an external ref-
erence clock. The burst type, length and latency
can be configured. The different configurations for
Synchronous Burst Read operations are de-
scribed in the Burst Configuration Register sec-
tion.
A valid Synchronous Burst Read operation begins
when the address is set on the Address Inputs,
Write Enable is High, V
IH
, and Chip Enable and
Latch Enable are Low, V
IL
, during the active edge
of the Clock. The address is latched on the first ac-
tive clock edge when Latch Enable is low, or on
the rising edge of Latch Enable, whichever occurs
first. The data becomes available for output after
the X-latency specified in the Burst Control Regis-
ter has expired. The output buffers are activated
by setting Output Enable Low, V
IL
. See Figure 7
for an example of a Synchronous Burst Read op-
eration.
The Burst Address Advance input and the Y-laten-
cy specified in the Burst Control Register deter-
mine whether the internal address counter is
advanced on the active edge of the Clock. When
the internal address counter is advanced the Data
Inputs/Outputs change to output the value for the
next address.
In Continuous Burst mode (Burst Length Bit M2-
M0 is set to ‘111’), one Burst Read operation can
access the entire memory sequentially and wrap
at the last address. The Burst Address Advance,
B, must be kept low, V
IL
, for the appropriate num-
ber of clock cycles. If Burst Address Advance, B,
is pulled High, V
IH
, the Burst Read will be sus-
pended.
In Continuous Burst Mode, if the starting address
is not associated with a page (4 Word or 2 Double
Word) boundary the Valid Data Ready, R, output
goes Low, V
IL
, to indicate that the data will not be
ready in time and additional wait-states are re-
quired. The Valid Data Ready output timing (bit
M8) can be changed in the Burst Configuration
Register.
When using the x32 Bus Width certain X-latencies
are not valid and must not be used; see Table 5,
Burst Configuration Register.
The Synchronous Burst Read timing diagrams
and AC Characteristics are described in the AC
and DC Parameters section. See Figures 19, 20
and Table 22.
Synchronous Pipelined Burst Read.
Synchro-
nous Burst Read operations can be overlapped to
avoid or reduce the X-latency. Pipelined opera-
tions should only be used with Burst Configuration
Register bit M9 = 0 (Y-latency setting).
A valid Synchronous Pipelined Burst Read opera-
tion occurs during a Synchronous Burst Read op-
eration when the new address is set on the
Address Inputs and a Low pulse is applied to Latch
Enable. The data for the new address becomes
valid after the X-latency specified in the Burst Con-
figuration Register has expired.
For optimum operation the address should be
latched on the correct clock cycle. Table 4 gives
the clock cycle for each valid X- and Y-latency set-
ting. Only these settings are valid, other settings
must not be used. There is always one Y-Latency
period where the data is not valid. If the address is
latched later than the clock cycle specified in Ta-
bles 4 then additional cycles where the data is not
valid are inserted. See Figure 8 for an example of
a Synchronous Pipelined Burst Read operation.
Here the X-latency is 8, the Y-latency is 1 and the
burst length is 4; the first address is latched on cy-
cle 1 while the next address is latched on cycle 6,
as shown in Table 4.
Synchronous Pipelined Burst Read operations
should only be performed on Burst Lengths of 4 or
8 with a x16 Bus Width or a Burst Length of 4 with
a x32 Bus Width.
Suspending a Pipelined Synchronous Burst Read
operation is not recommended.
Synchronous Burst Read Suspend.
During
Synchronous Burst Read operation it is possible to
suspend the operation, freeing the data bus for
other higher priority devices.
A valid Synchronous Burst Read operation is sus-
pended when both Output Enable and Burst Ad-
dress Advance are High, V
IH
. The Burst Address
Advance going High, V
IH
, stops the burst counter
and the Output Enable going High, V
IH
, inhibits the
data outputs. The Synchronous Burst Read oper-
ation can be resumed by setting Output Enable
Low. See Figure 7 for an example of a Synchro-
nous Burst Read Suspend operation.
a
相關(guān)PDF資料
PDF描述
M58LW128B150ZA1F 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA1T 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA6E 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA6F 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA6T 128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58LW128B150ZA1F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA1T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA6E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA6F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
M58LW128B150ZA6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:128 Mbit 8Mb x16 or 4Mb x32, Uniform Block, Burst 3V Supply Flash Memories
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