參數(shù)資料
型號: M58WR032FB70ZB6
廠商: 意法半導體
英文描述: 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
中文描述: 32兆位(含2Mb × 16,多銀行,突發(fā))1.8V電源快閃記憶體
文件頁數(shù): 27/86頁
文件大?。?/td> 1306K
代理商: M58WR032FB70ZB6
27/86
M58WR032FT, M58WR032FB
(no wrap). The Wrap Burst bit is used to select be-
tween wrap and no wrap. When the Wrap Burst bit
is set to ‘0’ the burst read wraps; when it is set to
‘1’ the burst read does not wrap.
Burst length Bits (CR2-CR0)
The Burst Length bits set the number of Words to
be output during a Synchronous Burst Read oper-
ation as result of a single address latch cycle.
They can be set for 4 Words, 8 Words, 16 Words
or continuous burst, where all the words are read
sequentially.
In continuous burst mode the burst sequence can
cross bank boundaries.
In continuous burst mode or in 4, 8, 16 Words no-
wrap, depending on the starting address, the de-
vice asserts the WAIT output to indicate that a de-
lay is necessary before the data is output.
If the starting address is aligned to a 4 Word
boundary no wait states are needed and the WAIT
output is not asserted.
If the starting address is shifted by 1,2 or 3 posi-
tions from the four word boundary, WAIT will be
asserted for 1, 2 or 3 clock cycles when the burst
sequence crosses the first 16 Word boundary, to
indicate that the device needs an internal delay to
read the successive words in the array. WAIT will
be asserted only once during a continuous burst
access. See also
Table 10., Burst Type Definition
.
CR14, CR5
and
CR4
are reserved for future use.
Table 9. Configuration Register
Bit
Description
Value
Description
CR15
Read Select
0
Synchronous Read
1
Asynchronous Read (Default at power-on)
CR14
Reserved
CR13-CR11
X-Latency
010
2 clock latency
011
3 clock latency
100
4 clock latency
101
5 clock latency
111
Reserved (default)
Other configurations reserved
CR10
Wait Polarity
0
WAIT is active Low
1
WAIT is active high (default)
CR9
Data Output
Configuration
0
Data held for one clock cycle
1
Data held for two clock cycles (default)
CR8
Wait Configuration
0
WAIT is active during wait state
1
WAIT is active one data cycle before wait state (default)
CR7
Burst Type
0
Interleaved
1
Sequential (default)
CR6
Valid Clock Edge
0
Falling Clock edge
1
Rising Clock edge (default)
CR5-CR4
Reserved
CR3
Wrap Burst
0
Wrap
1
No Wrap (default)
CR2-CR0
Burst Length
001
4 Words
010
8 Words
011
16 Words
111
Continuous (CR7 must be set to ‘1’) (default)
相關(guān)PDF資料
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M58WR032FB70ZB6E 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB70ZB6F 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB70ZB6T 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB80ZB6 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB80ZB6E 32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M58WR032FB70ZB6E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB70ZB6F 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB70ZB6T 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB80ZB6 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory
M58WR032FB80ZB6E 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:32 Mbit (2Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory