參數(shù)資料
型號(hào)： M5913B1
廠商： 意法半導(dǎo)體
元件分類： Codec
英文描述： COMBINED SINGLE CHIP PCM CODEC AND FILTER
中文描述： 組合單芯片的PCM編解碼器和過濾器
文件頁數(shù)： 16/17頁
文件大?。?/td> 220K
代理商： M5913B1
Symbol
Parameter
Test Conditions
Min.
Typ.
Max
Unit
POWER DISSIPATION All measurements made at fDCLK = 2.048MHz, outputs unloaded
ICC1
VCC Operating Current
6
10
mA
IBB1
VBB Operating Current
6
9
mA
ICC0
VCC Power Down Current
PDN
≤ VIL ; after 10s
40
300
A
IBB0
VBB Power Down Current
PDN
≤ VIL ; after 10s
40
300
A
ICCS
VCC Standby Current
FSX,FSR
≤ VIL ; after 30ms
300
600
A
IBBS
VBB Standby Current
FSX,FSR
≤ VIL ; after 30ms
40
300
A
PD1
Operating Power Dissipation
60
100
mW
PD0
Power Down Dissipation
PDN
≤ VIL ; after 10s
0.4
3
mW
PST
Standby Power Dissipation
FSX, FSR
≤ VIL ; after 30ms
1.7
5
mW
ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE
IBX1
Input Leakage Current, VFXI+, VFXI-
-2.17V
≤ VIN ≤ 2.17V
100
nA
RIXI
Input Resistance, VFXI+, VFXI-
10
M
VOSXI
Input Offset Voltage, VFXI+, VFXI-
25
mV
CMRR
Common Mode Rejection, VFXI+, VFXI-
-2.17V
≤ VIN ≤ 2.17V
55
dB
AVOL
DC Open Loop Voltage Gain, GSX
RL = 10K
5000
20.000
fC
Open Loop Unity Gain Bandwidth, GSX
1MHz
VOXI
Output Voltage Swing GSX
RL
≥ 10k
– 2.17
2.17
V
CLXI
Load Capacitance, GSX
50
pF
RLXI
Minimum Load Resistance, GSX
10
k
ANALOG INTERFACE, RECEIVE FILTER DRIVER AMPLIFIER STAGE
RORA
Output Resistance, PWRO+, PWRO-
1
VOSRA
Single-ended Output DC Offset,
PWRO+, PWRO-
Relative to GRDA
-150
75
150
mV
CLRA
Load Capacitance, PWRO+, PWRO-
100
pF
DC CHARACTERISTICS (continued)
AC CHARACTERISTICS - TRANSMISSION PARAMETERS
Unless otherwie noted, the analog input is a 0dBm0, 1020Hz sine wave
1. Input amplifier is set for unity
gain, noninverting. The digital inputs is a PCM bit stream generated by passing a 0dBm0, 1020Hz sine
wave through an ideal encoder. Receive output is measured single ended, maximum gain configuration
2.
All output levels are (sin X)/X corrected.
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
GAIN AND DYNAMIC RANGE
EmW
Encoder Milliwatt Response
(transmit gain tolerance)
Tamb =25
°C, VBB = – 5V,
VCC =+ 5V
-0.15
± 0.04 +0.15
dBm0
EmWTS
EmW Variation with Temperature and
Supplies
± 5% Supplies, 0 to 70°C
Relative to Nominal
Conditions
-0.12
+0.12
dB
DmW
Digital Milliwatt Response
(receive gain tolerance)
Tamb =25
°C; VBB = – 5V,
VCC =+ 5V
-0.15
± 0.04 +0.15
dBm0
DmWTS
DmW Variation with Temperature and
Supplies
± 5%, 0 to 70°C
-0.08
+0.08
dB
0TLP1X
Zero Transmission Level Point
Transmit Channel (0dBm0)
-law
Referenced to 600
Referenced to 900
+ 2.76
+ 1.00
dBm
0TLP2X
Zero Transmission Level Point
Transmit Channel (0dBm0) A-law
Referenced to 600
Referenced to 900
+ 2.79
+ 1.03
dBm
0TLP1R
Zero Receive Level Point
Receive Channel (0dBm0)
-law
Referenced to 600
Referenced to 900
+ 5.76
+ 4.00
dBm
0TLP2R
Zero Transmission Level Point
Transmit Channel (0dBm0)) A-law
Referenced to 600
Referenced to 900
+ 5.79
+ 4.03
dBm
M5913
8/17
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