- 您現(xiàn)在的位置：買賣IC網 > PDF目錄19675 > M5LV-128/120-7YI (Lattice Semiconductor Corporation)IC CPLD 128MC 120I/O 160PQFP PDF資料下載
參數(shù)資料
| 型號： | M5LV-128/120-7YI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 2/42頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 128MC 120I/O 160PQFP |
| 標準包裝： | 24 |
| 系列： | MACH® 5 |
| 可編程類型： | 系統(tǒng)內可編程 |
| 最大延遲時間 tpd(1)： | 7.5ns |
| 電壓電源 - 內部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 128 |
| 輸入/輸出數(shù)： | 120 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 160-BQFP |
| 供應商設備封裝： | 160-PQFP（28x28） |
| 包裝： | 托盤 |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
10
MACH 5 Family
MULTIPLE I/O AND DENSITY OPTIONS
The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers to choose
a device close to their logic density and I/O requirements, thus minimizing costs. For the same package type,
every density has the same pin-out. With proper design considerations, a design can be moved to a higher or
lower density part as required.
IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY
Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard. This
allows functional testing of the circuit board on which the device is mounted through a serial scan path that
can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and
loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition,
these devices can be linked into a board-level serial scan path for more complete board-level testing.
IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING
Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower
inventory levels, higher quality, and the ability to make in-field modifications. All MACH 5 devices provide in-
system programming (ISP) capability through their IEEE 1149.1-compliant Boundary Scan Test Access Port.
By using the IEEE 1149.1-compliant Boundary Scan Test Access Port as the communication interface
through which ISP is achieved, customers get the benefit of a standard, well-defined interface.
MACH 5 devices can be programmed across the commercial temperature and voltage range. The PC-based
LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO software takes the
JEDEC file output produced by design implementation software, along with information about the Boundary
Scan chain, and creates a set of vectors that are used to drive the Boundary Scan chain. LatticePRO software
can use these vectors to drive a Boundary Scan chain via the parallel port of a PC. Alternatively, LatticePRO
software can output files in formats understood by common automated test equipment. This equipment can
then be used to program MACH 5 devices during the testing of a circuit board.
PCI COMPLIANT
MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification
version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The
3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above
VCC because of their 5-V input tolerant feature. MACH 5 devices provide the speed, drive, density, output
enables and I/Os for the most complex PCI designs.
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關PDF資料 |
PDF描述 |
|---|---|
| MIC5211-3.6BM6 TR | IC REG LDO 3.6V 50MA SOT23-6 |
| V150A3V3E264BF | CONVERTER MOD DC/DC 3.3V 264W |
| L717DE09P | CONN DSUB PLUG 9POS SLD CUP GOLD |
| M5LV-128/120-5YC | IC CPLD 128MC 120I/O 160PQFP |
| EEC06DREN-S13 | CONN EDGECARD 12POS .100 EXTEND |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5LV-256/104-10AC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10AI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HC | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10HI | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture |
| M5LV-256/104-10VC | 功能描述:CPLD - 復雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復。