參數(shù)資料
型號(hào)： M5LV-128/68-12VI
廠商： Lattice Semiconductor Corporation
文件頁(yè)數(shù)： 34/42頁(yè)
文件大?。?/td> 0K
描述： IC CPLD 128MC 68I/O 100TQFP
標(biāo)準(zhǔn)包裝： 90
系列： MACH® 5
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時(shí)間 tpd(1)： 12.0ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 128
輸入/輸出數(shù)： 68
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
4
MACH 5 Family
and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test
Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block
interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the
segments together. The only logic difference between any two MACH 5 devices is the number of segments.
Therefore, once a designer is familiar with one device, consistent performance can be expected across the
entire family. All devices have four clock pins available which can also be used as logic inputs.
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an
independent PAL device, it has superior control and logic generation capabilities.
◆ I/O cells
◆ Product-term array and Logic Allocator
◆ Macrocells
◆ Register control generator
◆ Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local feedback.
If the I/O is used in another PAL block, the
interconnect feeder assigns a block interconnect line to that
signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide
connections between any two signals in a device. The
block feeder assigns block interconnect lines and local
feedback lines to the PAL block inputs.
Block
Interconnect
4
CLK
Block:
16 MCs
Segment:
4 Blocks
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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M5LV-128/68-10VC IC CPLD 128MC 68I/O 100TQFP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
M5LV-256/104-10AC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10AI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HC 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10HI 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:Fifth Generation MACH Architecture
M5LV-256/104-10VC 功能描述:CPLD - 復(fù)雜可編程邏輯器件 PROGRAM HI DENSITY CPLD RoHS:否 制造商:Lattice 系列: 存儲(chǔ)類型:EEPROM 大電池?cái)?shù)量:128 最大工作頻率:333 MHz 延遲時(shí)間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100
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