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參數(shù)資料
| 型號： | M5LV-512/160-10YI |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 10/42頁 |
| 文件大小： | 0K |
| 描述： | IC CPLD 512MC 160I/O 208PQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MACH® 5 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 160 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
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18
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-384/XXX
Macrocells
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73
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Logic
Array
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Logic
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Control
Generator
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32
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Generator
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32
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Generator
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AND
Logic
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Generator
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Macrocells
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Logic
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Logic
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Macrocells
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16
32
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7
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Generator
64
PT
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I/O
Cells
16
32
7
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2
32
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Control
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S
E
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CLK0
CLK1
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SEGMENT
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SEGMENT
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SEGMENT
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SEGMENT
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I 0
I 1
I 2
Macrocells
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Generator
64
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I/O
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16
32
7
PT
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2
32
16
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Generator
64
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OE
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32
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I/O
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64
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AND
Logic
Array
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Logic
Allocator
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Control
Generator
64
PT
2
PT
OE
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32
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PT
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16
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AND
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IN
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SEGMENT
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32
7
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2
32
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Control
Generator
64
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OE
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32
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PT
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2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
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Logic
Allocator
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Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Block
A/Macrocells
0-15
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D/Macrocells
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0-15
Block
Interconnect
I 3
SEGMENT
4
20446G-011
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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