- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄19582 > M5LV-512/256-10SAC (Lattice Semiconductor Corporation)IC CPLD 512MC 256I/O 352SBGA PDF資料下載
參數(shù)資料
| 型號： | M5LV-512/256-10SAC |
| 廠商： | Lattice Semiconductor Corporation |
| 文件頁數(shù)： | 34/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CPLD 512MC 256I/O 352SBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | MACH® 5 |
| 可編程類型： | 系統(tǒng)內(nèi)可編程 |
| 最大延遲時間 tpd(1)： | 10.0ns |
| 電壓電源 - 內(nèi)部： | 3 V ~ 3.6 V |
| 宏單元數(shù)： | 512 |
| 輸入/輸出數(shù)： | 256 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 352-LBGA |
| 供應(yīng)商設(shè)備封裝： | 352-SBGA（35x35） |
| 包裝： | 托盤 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
4
MACH 5 Family
and both the 3.3-V and the 5-V device versions are in-system programmable through an IEEE 1149.1 Test
Access Port (TAP) interface.
FUNCTIONAL DESCRIPTION
The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block
interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the block
interconnect is called a segment. The second level of interconnect, the segment interconnect, ties all of the
segments together. The only logic difference between any two MACH 5 devices is the number of segments.
Therefore, once a designer is familiar with one device, consistent performance can be expected across the
entire family. All devices have four clock pins available which can also be used as logic inputs.
The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block resembles an
independent PAL device, it has superior control and logic generation capabilities.
◆ I/O cells
◆ Product-term array and Logic Allocator
◆ Macrocells
◆ Register control generator
◆ Output enable generator
I/O Cells
The I/Os associated with each PAL block have a path directly back to that PAL block called
local feedback.
If the I/O is used in another PAL block, the
interconnect feeder assigns a block interconnect line to that
signal. The interconnect feeder acts as an input switch matrix. The block and segment interconnects provide
connections between any two signals in a device. The
block feeder assigns block interconnect lines and local
feedback lines to the PAL block inputs.
Block
Interconnect
4
CLK
Block:
16 MCs
Segment:
4 Blocks
Segment Interconnect
20446G-001
Figure 1. MACH 5 Block Diagram
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-B0R-CY-F4 | CONVERTER MOD DC/DC 7.5V 50W |
| M5-512/256-12SAI | IC CPLD ISP 512MC 256IO 352SBGA |
| VI-B0R-CY-F3 | CONVERTER MOD DC/DC 7.5V 50W |
| EPM7032LC44-6 | IC MAX 7000 CPLD 32 44-PLCC |
| VI-B0R-CY-F2 | CONVERTER MOD DC/DC 7.5V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M | 功能描述:XLR 連接器 5P ADAPT RECEPTACLE RoHS:否 制造商:Neutrik 標(biāo)準(zhǔn):Standard XLR 產(chǎn)品類型:Connectors 型式:Female 位置/觸點數(shù)量:3 端接類型:Solder 安裝風(fēng)格:Cable 方向:Vertical |
| M-5M | 制造商:SMC 功能描述:Fitting manifold 9 port Rc1/8 to M5 |
| M5M1 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MEDIUM CURRENT SILICON RECTIFIERS |
| M5M27C102J15 | 制造商:MITSUBISHI 功能描述:* |
| M5M27C102JK-15 | 制造商:Mitsubishi Electric 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。