參數(shù)資料
型號： M5LV-512/256-6SAC
廠商： Lattice Semiconductor Corporation
文件頁數(shù)： 10/42頁
文件大?。?/td> 0K
描述： IC CPLD 512MC 256I/O 352SBGA
標準包裝： 24
系列： MACH® 5
可編程類型： 系統(tǒng)內(nèi)可編程
最大延遲時間 tpd(1)： 6.5ns
電壓電源 - 內(nèi)部： 3 V ~ 3.6 V
宏單元數(shù)： 512
輸入/輸出數(shù)： 256
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 352-LBGA
供應(yīng)商設(shè)備封裝： 352-SBGA（35x35）
包裝： 托盤
18
MACH 5 Family
BLOCK DIAGRAM — M5(LV)-384/XXX
Macrocells
64
x
73
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Logic
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Generator
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Allocator
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Generator
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AND
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Interconnect
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Generator
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Generator
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Macrocells
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32
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Logic
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Generator
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I/O
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AND
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Control
Generator
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PT
2
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OE
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32
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PT
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2
32
16
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73
AND
Logic
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Block
A/Macrocells
0-15
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Interconnect
Macrocells
64
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73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
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OE
16
32
7
PT
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32
16
I/O
Cells
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73
AND
Logic
Array
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Logic
Allocator
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Control
Generator
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PT
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PT
OE
16
32
7
PT
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32
16
I/O
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x
73
AND
Logic
Array
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Logic
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Interconnect
S
E
G
M
E
N
T
CLK0
CLK1
CLK2
CLK3
4
SEGMENT
0
SEGMENT
5
SEGMENT
2
SEGMENT
1
I 0
I 1
I 2
Macrocells
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73
AND
Logic
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Allocator
Control
Generator
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PT
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PT
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I/O
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7
PT
7
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32
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Macrocells
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73
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Logic
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Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
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OE
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32
7
PT
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I/O
Cells
64
x
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AND
Logic
Array
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Logic
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Control
Generator
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OE
16
32
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73
AND
Logic
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Interconnect
IN
T
E
R
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T
SEGMENT
3
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PT
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32
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Macrocells
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AND
Logic
Array
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Logic
Allocator
Control
Generator
64
PT
2
PT
OE
I/O
Cells
16
32
7
PT
7
2
32
16
Macrocells
Control
Generator
64
PT
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PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
and
Logic
Allocator
Macrocells
Control
Generator
64
PT
2
PT
OE
16
32
7
PT
7
2
32
16
I/O
Cells
64
x
73
AND
Logic
Array
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Logic
Allocator
Block
A/Macrocells
0-15
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D/Macrocells
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B/Macrocells
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Interconnect
I 3
SEGMENT
4
20446G-011
Select
devices
have
been
discontinued.
See
Ordering
Information
section
for
product
status.
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