參數(shù)資料
型號: M5M29GB640C3TTC-12
廠商: Electronic Theatre Controls, Inc.
英文描述: 3.3V ONLY FLASHMEMORY
中文描述: 3.3只FLASHMEMORY
文件頁數(shù): 4/7頁
文件大?。?/td> 635K
代理商: M5M29GB640C3TTC-12
5
P/N:PM0900
M5M29GB640VP
REV. 0.3, NOV. 21, 2002
Table 1. Pin Description
Symbol
A0-A21
Type
input
Description and Function
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-
gram command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
Activates the device's control logic, input buffers, and sense amplifiers. CE high de-
selects the memory device and reduce power consumption to standby level. CE is
active low.
Reset Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,
which drives the outputs to High Z, resets the WSM and minimizes current level.
When RP=VIH, the device is normal operation. When RP transition the device defaults
to the read array mode.
Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The
data and address is latched WE on the rising edge of the second WE pulse.
DQ0-DQ15
input/output
CE
input
RP
input
WE
input
OE
WP
input
input
Output enable: gates the device's outputs during a real cycle.
Write protect: when WP is VIL, the boot sectors cannot be written or erased. When WP
is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter
and main sectors.
Device power supply: (2.7V~3.6V).
I/O Power Supply: supplies for input/output buffers. (Refer to section 6.2.6)
Ground voltage: all the GND pin shall not be connected.
VCC
VCCQ
GND
supply
input
supply
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