參數(shù)資料
型號： M5M44260CJ-7S
廠商： Mitsubishi Electric Corporation
英文描述： FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
中文描述： 快速頁面模式4194304位（262144字由16位）動態(tài)隨機(jī)存儲器
文件頁數(shù)： 28/29頁
文件大小： 283K
代理商： M5M44260CJ-7S
FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CJ,TP-5,-6,-7,-5S,-6S,-7S
MITSUBISHI LSIs
M5M44260CJ,TP-5,-5S : Under development
Switching from read/write operation to self refresh operation.
The time interval from the falling edge of RAS signal in the last
CBR refresh cycle during read/write operation period to the
falling edge of RAS signal at the start of self refresh operation
should be set within t
NSD
(shown in table 2).
Note 28 : Self refresh sequence
Two refreshing methods should be used properly depending on
the low pulse width (t
RASS
) of RAS signal during self refresh
period.
1. Distributed refresh during Read/Write operation
(A) Timing Diagram
Read / Write Cycle
Self Refresh Cycle
Read / Write Cycle
t
NSD
t
RASS
≥
100μs
t
SND
last
refresh cycle
first
refresh cycle
Table 2
Definition of CBR distributed refresh
(Including extended refresh)
The CBR distributed refresh performs more than 512
constant period (250μs max.) CBR cycles within 128 ms.
Switching from self refresh operation to read/write operation.
The time interval from the rising edge of RAS signal at the
end of self refresh operation to the falling edge of RAS signal
in the first CBR refresh cycle during read/write operation
period should be set within t
SND
(shown in table 2).
Switching from read/write operation to self refresh operation.
The time interval t
NSD
from the falling edge of RAS signal in
the last RAS only refresh cycle during read/write operation
period to the falling edge of RAS signal at the start of self
refresh operation should be set within 16μs.
Switching from self refresh operation to read/write operation.
The time interval t
SND
from the rising edge of RAS signal at
the end of self refresh operation to the falling edge of RAS
signal in the first CBR refresh cycle during read/write
operation period should be set within 16μs.
RAS
Read / Write Cycle
CBR distributed
refresh
RAS only
distributed refresh
Read / Write
Self Refresh
t
NSD
≤
16μs
t
SND
≤
16μs
(B) Definition of distributed refresh
t
REF
t
REF
/ 512
refresh
cycle
read/write
cycles
RAS
t
REF
/ 512
read/write
cycles
refresh
cycle
refresh
cycle
Note:
Hidden refresh may be used instead of CBR refresh.
RAS/CAS refresh may be used instead of RAS only refresh.
28
1.1 CBR distributed refresh
1.2 RAS only distributed refresh
All combinations of nine row address signals (A
0
~A
8
) are
selected during 512 constant period (16μs max.) RAS only
refresh cycles within 8.2 ms.
Definition of RAS only distributed refresh
t
NSD
≤
250μs
t
SND
≤
250μs
Self Refresh
Read / Write
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參數(shù)描述
M5M44260CTP-5 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-5S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-6 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
M5M44260CTP-6S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM
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