參數(shù)資料
型號: M5M467800BJ-5
廠商: Mitsubishi Electric Corporation
英文描述: FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
中文描述: 快速頁面模式67108864位(16777216 - Word的4位)動態(tài)隨機(jī)存儲器
文件頁數(shù): 10/37頁
文件大小: 246K
代理商: M5M467800BJ-5
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467400/465400DJ,DTP -5,-6,-5S,-6S
M5M467800/465800DJ,DTP -5,-6,-5S,-6S
M5M465160DJ,DTP -5,-6,-5S,-6S
MITSUBISHI ELECTRIC
Aug. 1999
MITSUBISHI LSIs
(Rev. 1.0)
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 70 , Vcc=3.3 0.3V, Vss=0V, unless otherwise noted See notes 13,14)
C
Read and Refresh Cycles
Parameter
Symbol
Limits
Unit
Note 21: Either t
RCH
or t
RRH
must be satisfied for a read cycle.
Read cycle time
RAS low pulse width
CAS low pulse width
t
RC
t
RAS
t
CAS
0
t
CSH
t
RSH
t
RCS
CAS hold time after RAS low
RAS hold time after CAS low
Read Setup time before CAS low
Read hold time after CAS high
Read hold time after RAS high
(Note 21)
(Note 21)
t
RCH
t
RRH
t
RAL
t
OCH
0
t
ORH
Column address to RAS hold time
CAS hold time after OE low
RAS hold time after OE low
10000
10000
10000
10000
90
50
13
50
13
10
25
13
13
0
0
110
60
15
60
15
10
30
15
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Min
Max
ns
ns
Parameter
Symbol
Limits
Unit
M5M46X400D-5,5S
M5M46X800D-5,5S
M5M465160D-5,5S
Min
M5M46X400D-6,6S
M5M46X800D-6,6S
M5M465160D-6,6S
Min
Refresh cycle time
t
REF
64
64
128
ms
ms
Max
Max
RAS high pulse width
Delay time, RAS low to CAS low
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
(Note15)
(Note16)
(Note17)
45
30
0
40
20
10
10
10
15
10
15
0
0
37
25
0
30
18
5
7
8
13
8
13
0
0
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
(Note18)
(Note18)
(Note19)
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
t
DZO
t
CDD
t
ODD
t
T
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
128
Refresh cycle time (S-version only)
t
REF
ns
(Note19)
(Note20)
Delay time, OE high to data
Transition time
15
13
15
13
ns
ns
ns
50
1
50
1
10
Note 13: The timing requirements are assumed t
T
=5ns.
14: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
2.0V and 0.8V respectively.
15: t
RCD(max)
is specified as a reference point only. If t
RCD
is less than t
RCD(max),
access time is t
RAC.
If t
RCD
is greater than t
RCD(max),
access
time is controlled exclusively by t
CAC
or t
AA.
t
RCD(min)
is specified as t
RCD(min)
=t
RAH(min)
+2t
T
+t
ASC(min).
16: t
RAD(max)
is specified as a reference point only. If t
RAD
t
RAD(max)
and t
ASC
t
ASC(max),
access time is controlled exclusively by t
AA.
17: t
ASC(max)
is specified as a reference point only. If t
RCD
t
RCD(max)
and t
ASC
t
ASC(max),
access time is controlled exclusively by t
CAC.
18:
Either t
DZC
or t
DZO
must be satisfied.
19: Either t
CDD
or t
ODD
must be satisfied.
20: t
T
is measured between V
IH(min)
and V
IL(max).
V
IH(min)
and V
IL(max)
of the switching characteristics are
M5M46X400D-5,5S
M5M46X800D-5,5S
M5M465160D-5,5S
M5M46X400D-6,6S
M5M46X800D-6,6S
M5M465160D-6,6S
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