參數資料
型號: M5M467800DTP-5
廠商: Mitsubishi Electric Corporation
英文描述: FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
中文描述: 快速頁面模式67108864位(16777216 - Word的4位)動態(tài)隨機存儲器
文件頁數: 11/37頁
文件大?。?/td> 246K
代理商: M5M467800DTP-5
FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (8388608-WORD BY 8-BIT) DYNAMIC RAM
FAST PAGE MODE 67108864-BIT (4194304-WORD BY 16-BIT) DYNAMIC RAM
M5M467400/465400DJ,DTP -5,-6,-5S,-6S
M5M467800/465800DJ,DTP -5,-6,-5S,-6S
M5M465160DJ,DTP -5,-6,-5S,-6S
MITSUBISHI ELECTRIC
Aug. 1999
MITSUBISHI LSIs
(Rev. 1.0)
11
Write Cycle (Early Write and Delayed Write)
Parameter
Symbol
Read-Write and Read-Modify-Write Cycles
Limits
Parameter
Symbol
Limits
Unit
Read write/read modify write cycle time
RAS low pulse width
CAS low pulse width
t
RWC
t
RAS
t
CAS
t
CSH
t
RSH
t
RCS
CAS hold time after RAS low
RAS hold time after CAS low
Read setup time before CAS low
(Note22)
(Note23)
(Note23)
50
0
30
75
45
15
15
50
50
0
30
65
40
13
13
126
85
50
85
t
CWD
t
RWD
t
AWD
t
CWL
t
RWL
t
WP
Delay time, CAS low to W low
Delay time, RAS low to W low
Delay time, address to W low
CAS hold time after W low
RAS hold time after W low
(Note23)
10000
10000
10000
10000
150
95
95
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Min
Max
Min
Max
OE hold time after W low
ns
15
13
t
OEH
Write cycle time
RAS low pulse width
CAS low pulse width
t
WC
t
RAS
t
CAS
8
t
CSH
t
RSH
t
WCS
CAS hold time after RAS low
RAS hold time after CAS low
Write setup time before CAS low
Write hold time after CAS low
CAS hold time after W low
(Note 23)
t
WCH
t
CWL
t
RWL
t
WP
0
t
DS
t
DH
t
OEH
10000
10000
10000
10000
90
50
13
50
13
8
0
8
13
10
15
15
0
110
60
15
60
15
10
0
10
15
RAS hold time after W low
Write pulse width
Data setup time before CAS low or W low
Data hold time after CAS low or W low
OE hold time after W low
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
Min
Max
Min
Max
ns
13
13
Note 22: t
RWC
is specified as t
RWC(min)
=t
RAC(max)
+t
ODD(min)
+t
RWL(min)
+t
RP(min)
+4t
T.
23: t
WCS
, t
CWD
, t
RWD
and t
AWD
and, t
CPWD
are specified as reference points only. If t
WCS
t
WCS(min)
the cycle is an early write cycle and the
DQ pins will remain high impedance throughout the entire cycle. If t
CWD
t
CWD(min),
t
RWD
t
RWD (min),
t
AWD
t
AWD(min)
and t
CPWD
t
CPWD(min)
(for Fast Page mode cycle only), the cycle is a read-modify-write cycle and the DQ will contain the data read from the selected address.
If neither of the above condition (delayed write) is satisfied, the DQ (at access time and until CAS or OE goes back to V
IH
) is indetermi-
nate.
ns
t
DS
t
DH
8
0
8
10
0
10
Write pulse width
Data hold time after CAS low or W low
Data setup time before CAS low or W low
ns
ns
ns
ns
M5M46X400D-5,5S
M5M46X800D-5,5S
M5M465160D-5,5S
M5M46X400D-6,6S
M5M46X800D-6,6S
M5M465160D-6,6S
M5M46X400D-5,5S
M5M46X800D-5,5S
M5M465160D-5,5S
M5M46X400D-6,6S
M5M46X800D-6,6S
M5M465160D-6,6S
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M5M467800DTP-6S 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:FAST PAGE MODE 67108864-BIT (16777216-WORD BY 4-BIT) DYNAMIC RAM
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