- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370973 > M5M4V16G50DFP-8 (Mitsubishi Electric Corporation) 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM PDF資料下載
參數(shù)資料
| 型號： | M5M4V16G50DFP-8 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM |
| 中文描述： | 1,600（2 -銀行甲262144字× 32位）同步圖形RAM |
| 文件頁數(shù)： | 15/33頁 |
| 文件大?。?/td> | 167K |
| 代理商： | M5M4V16G50DFP-8 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁
M5M4V16G50DFP -8, -10, -12
Jan'97
Preliminary
MITSUBISHI LSIs
16M (2-BANK x 262144-WORD x 32-BIT) Synchronous Graphics RAM
MITSUBISHI ELECTRIC
SGRAM (Rev. 0.0)
POWER ON SEQUENCE
Before starting normal operation, the following power on sequence is necessary to prevent a SGRAM
from damaged or malfunctioning.
1. Apply power and start clock. Attempt to maintain CKE high, DQM0-3 high and NOP condition at
the inputs.
2. Maintain stable power, stable clock, and NOP input conditions for a minimum of 500μs.
3. Issue precharge commands for all banks. (PRE or PREA)
4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
After these sequence, the SGRAM is idle state and ready for normal operation.
MODE REGISTER
Burst Length, Burst Type and /CAS Latency can be programmed by setting the mode register (MRS). The
mode register stores these data until the next MRS command, which may be issued when both banks are in
idle state. After tRSC from a MRS command, the SGRAM is ready for new command.
0
1
BURST
TYPE
SEQUENTIAL
INTERLEAVED
CL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
CAS LATENCY
Operating Mode
Normal Operation
0
0
-
Burst Read and Single Write
All Others are Reserved
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
LTMODE
BT
BL
0
BL
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
BT= 0
BT= 1
1
2
4
8
4
8
/CS
/RAS
/CAS
/WE
A10, A9 -A0
CLK
V
A10
0
0
0
A7
0
0
-
A8
0
1
-
A9
0
0
-
A10
LVTTL
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
DSF
BURST LENGTH
Reserved
Reserved
Full Page
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M4V64S20ATP-10 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-10L | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-12 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8 | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
| M5M4V64S20ATP-8A | 64M (4-BANK x 4194304-WORD x 4-BIT) Synchronous DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M4V17400CTP-60 | 制造商:Mitsubishi Electric 功能描述: |
| M5M4V18165CJ-7S | 制造商:MITSUBI 功能描述:Electronic Component |
| M5M4V4169TP20 | 制造商:MITSU 功能描述: |
| M5M4V4265CJ | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
| M5M4V4265CJ-5 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:EDO (HYPER PAGE) MODE 4194304-BIT (262144-WORD BY 16-BIT) DYNAMIC RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。