- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370974 > M5M51008DVP-55H (Mitsubishi Electric Corporation) 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM PDF資料下載
參數(shù)資料
| 型號： | M5M51008DVP-55H |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | DRAM |
| 英文描述： | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| 中文描述： | 1048576位（131072 - Word的8位）的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 2/7頁 |
| 文件大小： | 61K |
| 代理商： | M5M51008DVP-55H |
MITSUBISHI LSIs
M5M51008BP,FP,VP,RV,KV,KR -55L,-70L,-10L,
-55LL,-70LL,-10LL
1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM
1997-3/25
MITSUBISHI
ELECTRIC
FUNCTION
The operation mode of the M5M51008B series are determined by
a combination of the device control inputs S
1
,S
2
,W and OE.
Each mode is summarized in the function table.
A write cycle is executed whenever the low level W overlaps with
the low level S
1
and the high level S
2
. The address must be set up
before the write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of W,S
1
or
S
2
,whichever occurs first,requiring the set-up and hold time
relative to these edge to be maintained. The output enable input
OE directly controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state, and the data
bus contention problem in the write cycle is eliminated.
A read cycle is executed by setting W at a high level and OE at a
low level while S
1
and S
2
are in an active state(S
1
=L,S
2
=H).
BLOCK DIAGRAM
A
B
A
A
S
C
D
B
D
CLOCK
GENERATOR
O
B
D
131072 WORDS
X 8 BITS
(1024 ROWS
X128 COLUMNS
X 8BLOCKS)
8
7
6
5
4
3
2
31
28
27
16
15
14
13
12
11
10
7
4
3
12
10
9
23
20
18
17
31
11
25
26
19
1
2
21
22
23
25
26
27
28
29
13
14
15
17
18
19
20
21
5
30
6
32
8
29
22
30
24
32
16
24
A4
A5
A6
A7
A12
A14
A16
A15
A13
A8
A0
A2
A3
A10
A1
A11
A9
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
W
S1
S2
OE
V
CC
GND
(0V)
* Pin numbers inside dotted line show those of TSOP
*
*
When setting S
1
at a high level or S
2
at a low level, the chip are
in a non-selectable mode in which both reading and writing are
disabled. In this mode, the output stage is in a high- impedance
state, allowing OR-tie with other chips and memory expansion by
S
1
and S
2
. The power supply current is reduced as low as the
stand-by current which is specified as I
CC3
or I
CC4
, and the
memory data can be held at +2V power supply, enabling battery
back-up operation during power failure or power-down operation in
the non-selected mode.
S
1
X
S
2
L
W
X
OE
X
Mode
DQ
I
CC
L
L
H
H
H
H
L
H
Non selection
Non selection High-impedance
Write
Read
High-impedance
Din
Dout
Active
Stand-by
Stand-by
High-impedance
Active
Active
DATA
INPUTS/
OUTPUTS
WRITE
CONTROL
INPUT
CHIP
SELECT
INPUTS
OUTPUT
ENABLE
INPUT
ADDRESS
INPUTS
FUNCTION TABLE
2
L
H
L
X
H
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M5M51008DVP-70H | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008BFP-10VL | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008BFP-10VLL | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008BFP-12VL | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
| M5M51008BVP-70VLL | 1048576-BIT(131072-WORD BY 8-BIT)CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M5M51008DVP-55H#ST | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 55ns 32-Pin TSOP-I T/R |
| M5M51008DVP-55H(#BT) | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 55ns 32-Pin TSOP-I Tube |
| M5M51008DVP55HI | 制造商:Renesas Electronics Corporation 功能描述: |
| M5M51008DVP-55HI | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Async Single 5V 1M-Bit 128K x 8 55ns 32-Pin TSOP-I |
| M5M51008DVP-55HI#BT | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。