MITSUBISHI LSIs
1048576-BIT(65536-WORD BY 16-BIT)CMOS STATIC RAM
M5M51R16AWG -10LI, -12LI, -15LI,
-10HI, -12HI, -15HI
MITSUBISHI
ELECTRIC
Aug.1. 1998
FUNCTION
2
The operation mode of the M5M51R16A series are
determined by a combination of the device control
inputs S, W, OE, BC1 and BC2. Each mode is
summarized in the function table.
A write cycle is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the
low level S. The address must be set up before the
write cycle and must be stable during the entire cycle.
The data is latched into a cell on the trailing edge of
W, BC1, BC2 or S, whichever occurs first, requiring
the set-up and hold time relative to these edge to be
maintained. The output enable input OE directly
controls the output stage. Setting the OE at a high
level, the output stage is in a high-impedance state,
and the data bus contention problem in the write cycle
is eliminated.
A read cycle is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S
are in an active state. (BC1 and/or BC2=L, S=L)
When setting BC1 at a high level and the other pins
are in an active state, upper-Byte are in a selectable
mode in which both reading and writing are enabled,
and lower -Byte are in a non-selectable mode. And
when setting BC2 at a high level and the other pins
are in an active state, lower-Byte are in a selectable
mode in which both reading and writing are enabled,
and upper -Byte are in a non-selectable mode.
When setting BC1 and BC2 at a high level or S at
a high level, the chips are in a non-selectable mode in
which both reading and writing are disabled.
In this mode, the output stage is in a high-impedance
state, allowing OR -tie with other chips and memory
expansion by BC1, BC2 and S. S, BC1 and BC2
control the power down feature. When S, BC1 and
BC2 go high, the power supply current is reduced as
low as the stand-by current which is specified as Icc3
or Icc4, and the memory data can be held at +1.0V
power supply, enabling battery back-up operation
during power-failure or power-down operation in the
non-selected mode.
(High-Z=High-impedance)
FUNCTION TABLE
Mode
Word Read
DQ1~8 DQ9~16
Dout
Icc
Non selection
L
X
X
X
X
X
High-Z
X
H
X
H
H
X
X
High-Z
Stand-by
Upper-Byte Write
(Lower-Byte Non selection)
H
H
L
L
X
H
X
Din
Active
Upper-Byte Read
(Lower-Byte Non selection)
L
L
High-Z
Dout
Active
H
L
H
High-Z
Active
Lower-Byte Write
(Upper-Byte Non selection)
L
H
L
High-Z
Din
Active
Lower-Byte Read
(Upper-Byte Non selection)
L
H
X
H
High-Z
High-Z Stand-by
High-Z
Dout
Active
L
High-Z
Word Write
L
L
L
Din
L
L
L
Dout
Active
H
L
L
High-Z
Active
Din
W OE
S
BC1 BC2
L
L
L
Output disable
Non selection
CLOCK
GENERATOR
65536 WORDS x16 BITS
( 512 ROWS
x 256 COLUMNS
x 8 BLOCKS )
ADDRESS
INPUTS
CHIP SELECT
INPUT
BC2
BC1
CONBYTE
INPUTS
WRITE CONTROL
INPUT
OUTPUT ENABLE
INPUT
DATA
INPUTS/
OUTPUTS
BLOCK DIAGRAM
A4D4
A3A4
A2B4
A1C4
A0A5
A15H5
A14F4
A13G4
A12H4
A8H2
A9F3
A10G3
A11H3
A7B3
A5 C3
A6A3
B5
G5
A2
B2
W
OE
S
A1
B6DQ1
C5DQ2
C6DQ3
D5DQ4
E5DQ5
F6 DQ6
F5 DQ7
G6DQ8
G1DQ9
F2DQ10
F1DQ11
E2DQ12
D2DQ13
C1DQ14
C2DQ15
B1DQ16
E1Vcc
E6 G(0V)
D1 G(0V)
Vcc
D6
E3 G(0V)