參數(shù)資料
型號: M5M5256DVP-15VXL-I
廠商: Mitsubishi Electric Corporation
英文描述: 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
中文描述: 262144位(32768 - Word的8位)的CMOS靜態(tài)RAM
文件頁數(shù): 4/7頁
文件大?。?/td> 63K
代理商: M5M5256DVP-15VXL-I
MITSUBISHI LSIs
262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM
MITSUBISHI
ELECTRIC
M5M5256DFP,VP,RV -10VLL,-12VLL,-15VLL,
-10VXL,-12VXL,-15VXL
'97.4.7
4
(2) READ CYCLE
(3) WRITE CYCLE
Symbol
Parameter
t
CR
t
a
(A)
Read cycle time
Address access time
Chip select access time
Output enable access time
Output disable time after /S high
Output disable time after /OE high
Output enable time after /S low
Output enable time after /OE low
Data valid time after address
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
t
a
(S)
t
a
(OE)
t
dis
(S)
t
dis
(OE)
t
en
(S)
t
en
(OE)
t
V
(A)
-15VLL, VXL
Min
150
AC ELECTRICAL CHARACTERISTICS
(Ta = 0~70°C, Vcc=2.7~3.6V, unless otherwise noted )
(1) MEASUREMENT CONDITIONS
Input pulse level···················V
IH
=2.2V,V
IL
=0.4V
Input rise and fall time··········5ns
Reference level····················V
OH
=V
OL
=1.5V
Output loads·························Fig.1,CL=30pF (-10VLL,-10VXL )
CL=50pF (-12VLL,-12VXL )
CL=100pF (-15VLL,-15VXL )
CL=5pF (for ten,tdis)
Transition is measured ±500mV from steady
state voltage. (for ten,tdis)
Max
120
10
10
10
Min
120
120
60
35
35
Max
100
10
10
10
Min
100
100
50
30
30
Max
-10VLL, VXL -12VLL, VXL
10
10
10
150
150
75
40
40
Symbol
Parameter
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Limits
Write cycle time
Write pulse width
Address setup time
Address setup time with respect to /W high
Chip select setup time
Data setup time
Data hold time
Write recovery time
Output disable time from /W low
Output disable time from /OE high
Output enable time from /W high
Output enable time from /OE low
Max
Min
150
90
-15VLL, VXL
-10VLL, VXL -12VLL, VXL
Max
100
70
0
80
80
40
0
0
35
35
Max
120
80
0
90
90
45
0
0
10
10
Min
30
30
10
10
Min
t
CW
t
w
(W)
t
su
(A)
t
su
(A-WH)
t
su
(S)
t
su
(D)
t
h
(D)
t
rec
(W)
t
dis
(W)
t
dis
(OE)
t
en
(W)
t
en
(OE)
40
40
0
100
100
50
0
0
10
10
Fig.1 Output load
(Including
scope and JIG)
DQ
L
C
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