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參數(shù)資料
| 型號： | M5M5V216ART |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 2097152位（131072字由16位）的CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 2/7頁 |
| 文件大?。?/td> | 134K |
| 代理商： | M5M5V216ART |
MITSUBISHI ELECTRIC
M5M5V216AWG
revision-01, ' 98.12.08
2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM
MITSUBISHI LSIs
FUNCTION TABLE
2
FUNCTION
The M5M5V216AWG is organized as 131,072-words by
16-bit. These devices operate on a single +2.7~3.6V power
supply, and are directly TTL compatible to both input and
output. Its fully static circuit needs no clocks and no
refresh, and makes it useful.
The operation mode are determined by a combination of
the device control inputs BC1 , BC2 , S , W and OE.
Each mode is summarized in the function table.
A write operation is executed whenever the low level W
overlaps with the low level BC1 and/or BC2 and the low
level S. The address(A0~A16) must be set up before the
write cycle and must be stable during the entire cycle.
A read operation is executed by setting W at a high level
and OE at a low level while BC1 and/or BC2 and S are in
an active state(S=L).
When setting BC1 at the high level and other pins are in
an active stage , upper-byte are in a selesctable mode in
which both reading and writing are enabled, and lower-byte
are in a non-selectable mode. And when setting BC2 at a
high level and other pins are in an active stage, lower-
byte are in a selectable mode and upper-byte are in a
non-selectable mode.
When setting BC1 and BC2 at a high level or S at a high
level, the chips are in a non-selectable mode in which both
reading and writing are disabled. In this mode, the output
stage is in a high-impedance state, allowing OR-tie with
other chips and memory expansion by BC1, BC2 and S.
The power supply current is reduced as low as 0.3μA(25 C,
typical), and the memory data can be held at +2V power
supply, enabling battery back-up operation during power
failure or power-down operation in the non-selected mode.
BLOCK DIAGRAM
Mode
H
L
W
X
X
X
H
X
H
High-Z
High-Z High-Z
Din
Dout
High-Z High-Z
High-Z
High-Z
S BC1 BC2
OE
X
X
DQ1~8
Non selection
DQ9~16
High-Z Standby
Icc
L
L
L
L
L
X
L
H
X
L
L
H
H
L
H
L
L
L
H
H
H
H
H
L
L
High-Z
High-Z
Active
Active
Active
Active
Active
Read
L
L
H
L
L
L
Active
Active
L
L
High-Z
Din
High-Z
Active
H
L
H
X
H
High-Z
L
L
Dout
H
L
L
Read
Dout
Active
L
Write
Din
H
High-Z
Non selection
Standby
Write
Write
Read
Din
Dout
MEMORY ARRAY
131072 WORDS
x 16 BITS
CLOCK
GENERATOR
A
0
A
1
A
15
A
16
S
BC1
BC2
W
OE
DQ
8
DQ
1
DQ
16
DQ
9
-
Vcc
GND
相關PDF資料 |
PDF描述 |
|---|---|
| M5M5V216ATP | Octal Buffers/Drivers With 3-State Outputs 20-TSSOP -40 to 85 |
| M5M5V216AWG-55HW | 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V216AWG-55L | 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V216AWG-55LI | 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V216AWG-55LW | 2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| M5M5V216ART-55HI | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V216ART-70HI | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V216ATP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:2097152-BIT (131072-WORD BY 16-BIT) CMOS STATIC RAM |
| M5M5V216ATP-55HI | 制造商:Renesas Electronics Corporation 功能描述: |
| M5M5V216ATP-55HI(#BT) | 制造商:Renesas Electronics Corporation 功能描述: |
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