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參數(shù)資料
| 型號： | M5M5Y5636TG-22 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM |
| 中文描述： | 18874368位（524288 - Word的36位）網(wǎng)絡(luò)的SRAM |
| 文件頁數(shù)： | 1/27頁 |
| 文件大?。?/td> | 212K |
| 代理商： | M5M5Y5636TG-22 |
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MITSUBISHI LSIs
M5M5Y5636TG – 25,22,20
18874368-BIT(524288-WORD BY 36-BIT) NETWORK SRAM
1
MITSUBISHI
ELECTRIC
Advanced Information
M5M5Y5636TG REV.0.0
DESCRIPTION
The M5M5Y5636TG is a family of 18M bit synchronous SRAMs
organized as 524288-words by 36-bit. It is designed to eliminate
dead bus cycles when turning the bus around between reads and
writes, or writes and reads. Mitsubishi's SRAMs are fabricated
with high performance, low power CMOS technology, providing
greater reliability. M5M5Y5636TG operates on a single 1.8V
power supply and are 1.8V CMOS compatible.
FEATURES
Fully registered inputs and outputs for pipelined operation
Fast clock speed: 250, 225, and 200 MHz
Fast access time: 2.6, 2.8, 3.2 ns
Single 1.8V +150/-100mV power supply V
DD
Separate V
DDQ
for 1.8V I/O
Individual byte write (BWa# - BWd#) controls may be tied
LOW
Single Read/Write control pin (W#)
Echo Clock outputs track data output drivers
ZQ mode pin for user-selectable output drive strength
2 User programmable chip enable inputs for easy depth
expansion
Linear or Interleaved Burst Modes
JTAG boundary scan support
APPLICATION
High-end networking products that require high bandwidth, such
as switches and routers.
PACKAGE
FUNCTION
Synchronous circuitry allows for precise cycle control triggered
by a positive edge clock transition.
Synchronous signals include : all Addresses, all Data Inputs,
all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV),
Byte Write Enables (BWa#, BWb#, BWc#, BWd#), Echo Clock
outputs (CQ1, CQ1#, CQ2, CQ2#) and Read/Write (W#). Write
operations are controlled by the eight Byte Write Enables (BWa#
- BWd#) and Read/Write(W#) inputs. All writes are conducted
with on-chip synchronous self-timed write circuitry.
The Echo Clocks are delayed copies of the RAM clock, CLK.
Echo Clocks are designed to track changes in output driver
delays due to variance in die temperature and supply voltage.
The ZQ pin supplied with selectable impedance drivers, allows
selection between nominal drive strength (ZQ LOW) for multi-
drop bus application and low drive strength (ZQ floating or HIGH)
point-to-point applications.
The sense of two User-Programmable Chip Enable inputs (E2,
E3), whether they function as active LOW or active HIGH inputs,
is determined by the state of the programming inputs, EP2 and
EP3.
The Linear Burst order (LBO#) is DC operated pin. LBO# pin
will allow the choice of either an interleaved burst, or a linear
burst.
All read, write and deselect cycles are initiated by the ADV
Low input. Subsequent burst address can be internally generated
as controlled by the ADV HIGH input.
PART NAME TABLE
Bump
Body Size
14mm X 22mm
Bump Pitch
1mm
M5M5Y5636TG
209(11X19) bump BGA
Part Name
Frequency
Access
Cycle
Active Current
(max.)
Standby Current
(max.)
20mA
20mA
20mA
M5M5Y5636TG -25
M5M5Y5636TG -22
M5M5Y5636TG -20
250MHz
225MHz
200MHz
2.6ns
2.8ns
3.2ns
4.0ns
4.4ns
5.0ns
400mA
380mA
360mA
2001.June Rev.0.0
Advanced Information
Notice: This is not final specification.
Some parametric limits are subject to change.
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PDF描述 |
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